A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (ESSCIRC, 2016)

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (ISSCC, 2016)

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (IEEE J. Solid State Circuits, 2016)

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (IEEE J. Solid State Circuits, 2017)

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (ISSCC, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. - Marc Erett; Declan Carey; Ronan Casey; James Hudner; Kevin Geary; Ted Lee; Mayank Raj; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; Haibing Zhao; et al. (CICC, 2019)

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (IEEE J. Solid State Circuits, 2019)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (VLSI Circuits, 2021)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2022)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)