SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. - Witold A. Pleskacz; Wieslaw Kuzmicz (ED&TC, 1995)

Extraction of critical areas for opens in large VLSI circuits. - Charles H. Ouyang; Witold A. Pleskacz; Wojciech Maly (DFT, 1996)

CAD at the Design-Manufacturing Interface. - Hans T. Heineken; Jitendra Khare; Wojciech Maly; Pranab K. Nag; Charles H. Ouyang; Witold A. Pleskacz (DAC, 1997)

Improved Yield Model for Submicron Domain. - Witold A. Pleskacz; Wojciech Maly (DFT, 1997)

Detection of Yield Trends. - Witold A. Pleskacz; Wojciech Maly; Hans T. Heineken (DFT, 1997)

Yield Estimation of VLSI Circuits with Downscaled Layouts. - Witold A. Pleskacz (DFT, 1999)

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. - Witold A. Pleskacz; Charles H. Ouyang; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Graphical user interface of FIESTA - software for faults identification and estimation of testability of VLSI circuits. - Mykola Blyzniuk; Taras Panchak; Wieslaw Kuzmicz; Witold A. Pleskacz (CCU, 2000)

Hierarchical defect-oriented fault simulation for digital circuits. - Mykola Blyzniuk; T. Cibáková; Elena Gramatová; Wieslaw Kuzmicz; M. Lobur; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ETW, 2000)

CMOS Standard Cells Characterization for Defect Based Testing. - Witold A. Pleskacz; Dominik Kasprowicz; Tomasz Oleszczak; Wieslaw Kuzmicz (DFT, 2001)

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. - Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ISQED, 2001)

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. - Mykola Blyzniuk; Irena Kazymyra; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2001)

CMOS Standard Cells Characterization for IDDQ Testing. - Witold A. Pleskacz; Tomasz Borejko; Wieslaw Kuzmicz (DFT, 2002)

Hierarchical test generation for combinational circuits with real defects coverage. - T. Cibáková; Mária Fischerová; Elena Gramatová; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2002)

Improvement of integrated circuit testing reliability by using the defect based approach. - Dominik Kasprowicz; Witold A. Pleskacz (Microelectron. Reliab., 2003)

Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. - Joachim Sudbrock; Jaan Raik; Raimund Ubar; Wieslaw Kuzmicz; Witold A. Pleskacz (DSD, 2005)

DOT: new deterministic defect-oriented ATPG tool. - Jaan Raik; Raimund Ubar; Joachim Sudbrock; Wieslaw Kuzmicz; Witold A. Pleskacz (ETS, 2005)

DefSim: CMOS Defects on Chip for Research and Education. - Witold A. Pleskacz; Tomasz Borejko; Andrzej Walkanis; Viera Stopjaková; Artur Jutman; Raimund Ubar (LATW, 2006)

Layout to Logic Defect Analysis for Hierarchical Test Generation. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Witold A. Pleskacz; Michal Rakowski (DDECS, 2007)

ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. - Zbigniew Piatek; Jerzy F. Kolodziejski; Witold A. Pleskacz (DDECS, 2007)

Power Dissipation in Basic Global Clock Distribution Networks. - Artur L. Sobczyk; Arkadiusz W. Luczyk; Witold A. Pleskacz (DDECS, 2007)

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. - Marcin J. Beresinski; Tomasz Borejko; Witold A. Pleskacz; Viera Stopjaková (DDECS, 2008)

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. - Tomasz Borejko; Witold A. Pleskacz (DDECS, 2008)

Various MDCT implementations in 0.35µm CMOS. - Peter Malík; Marcel Baláz; Martin Simlastík; Arkadiusz W. Luczyk; Witold A. Pleskacz (DDECS, 2008)

Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. - Artur L. Sobczyk; Arkadiusz W. Luczyk; Witold A. Pleskacz (DDECS, 2008)

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. - Witold A. Pleskacz; Maksim Jenihhin; Jaan Raik; Michal Rakowski; Raimund Ubar; Wieslaw Kuzmicz (DSD, 2008)

Characterization of CMOS sequential standard cells for defect based voltage testing. - Andrzej Wielgus; Witold A. Pleskacz (EWDTS, 2008)

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. - Witold A. Pleskacz; Viera Stopjaková; Tomasz Borejko; Artur Jutman; Andrzej Walkanis (IEEE Trans. Ind. Electron., 2008)

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. - Jacek Gradzki; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2009)

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. - Peter Malík; Michal Ufnal; Arkadiusz W. Luczyk; Marcel Baláz; Witold A. Pleskacz (DDECS, 2009)

Enhanced LEON3 core for superscalar processing. - Krzysztof Marcinek; Arkadiusz W. Luczyk; Witold A. Pleskacz (DDECS, 2009)

A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. - Jacek Gradzki; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2010)

A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. - Jakub Kopanski; Witold A. Pleskacz; Dariusz Pienkowski (DDECS, 2011)

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. - Michal Lukaszewicz; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

CAD tool for PLL Design. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2011)

AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. - Krzysztof Marcinek; Witold A. Pleskacz (DDECS, 2012)

LC-VCO design automation tool for nanometer CMOS technology. - Krzysztof Siwiec; Tomasz Borejko; Witold A. Pleskacz (DDECS, 2012)

Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. - Krzysztof Siwiec; Aleksander Koter; Witold A. Pleskacz (DDECS, 2013)

ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model. - Krzysztof Marcinek; Witold A. Pleskacz (Microprocess. Microsystems, 2013)

Multistage low ripple charge pump. - Andrzej Grodzicki; Witold A. Pleskacz (DDECS, 2014)

Implementation of the Bluetooth receiver RF front-end in the CMOS-RF 130 nm technology. - Daniel Pietron; Krzysztof Siwiec; Jakub Kopanski; Witold A. Pleskacz (MIXDES, 2014)

Simulink model of GFSK demodulator based on time-to-digital converter. - Lukasz Wiechowski; Krzysztof Siwiec; Jakub Kopanski; Witold A. Pleskacz (MIXDES, 2014)

A Low Ripple Current Mode Voltage Doubler. - Andrzej Grodzicki; Witold A. Pleskacz (DDECS, 2015)

Implementation of the ADELITE Microcontroller for Biomedical Applications. - Krzysztof Marcinek; Maciej Plasota; Andrzej Wielgus; Witold A. Pleskacz (DDECS, 2015)

UVM-based Verification of Bluetooth Low Energy Controller. - Maciej Moskala; Patryk Kloczko; Marek Cieplucha; Witold A. Pleskacz (DDECS, 2015)

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology. - Mariusz Derlecki; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2015)

Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications. - Aleh Halauko; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2015)

A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring. - Krzysztof Siwiec; Krzysztof Marcinek; Tomasz Borejko; Adam Jarosz; Jakub Kopanski; Ewa Kurjata-Pfitzner; Pawel Narczyk; Maciej Plasota; Andrzej Wielgus; Witold A. Pleskacz (MIXDES, 2015)

Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. - Igor Butryn; Krzysztof Siwiec; Jakub Kopanski; Witold A. Pleskacz (DDECS, 2016)

Precision human body temperature measurement based on thermistor sensor. - Pawel Narczyk; Krzysztof Siwiec; Witold A. Pleskacz (DDECS, 2016)

BioSoC: Highly integrated System-on-Chip for health monitoring. - Krzysztof Siwiec; Krzysztof Marcinek; Piotr Boguszewicz; Tomasz Borejko; Aleh Halauko; Adam Jarosz; Jakub Kopanski; Ewa Kurjata-Pfitzner; Pawel Narczyk; Maciej Plasota; Andrzej Wielgus; Witold A. Pleskacz (DDECS, 2016)

Dedicated chip for pulse oximetry measurements. - Cezary Kolacinski; Jerzy Wasowski; Andrzej Szymanski; Adam Jarosz; Ewa Kurjata-Pfitzner; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (EWDTS, 2016)

New architecture of the object-oriented functional coverage mechanism for digital verification. - Marek Cieplucha; Witold A. Pleskacz (IVSW, 2016)

The integrated transmitter and receiver modules for pulse oximeter system. - Cezary Kolacinski; Andrzej Szymanski; Adam Jarosz; Ewa Kurjata-Pfitzner; Jerzy Wasowski; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2016)

A low sampling frequency switched capacitor low-pass filter for wireless receivers. - Jakub Kopanski; Lukasz Wiechowski; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2016)

Monitoring of dynamic movements using acceleration measurements. - Konrad Neneman; Arkadiusz W. Luczyk; Witold A. Pleskacz (MIXDES, 2016)

Architecture and design of a Bluetooth Low Energy Controller. - Pawel Wiecha; Marek Cieplucha; Patryk Kloczko; Witold A. Pleskacz (MIXDES, 2016)

Analog front-end for precise human body temperature measurement. - Pawel Narczyk; Krzysztof Siwiec; Witold A. Pleskacz (DDECS, 2017)

Principal component analysis of accelerations in human dynamic movements: A sample set length effect study. - Arkadiusz W. Luczyk; Konrad Neneman; Witold A. Pleskacz (MIXDES, 2017)

Temperature calibration technique based on on-chip resistor. - Pawel Narczyk; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2017)

Importance of on-chip inductor modeling in radio frequency integrated circuits. - Daniel Pietron; Tomasz Borejko; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2017)

EIA/TIA-485 transceiver in standard 130 nm CMOS technology. - Michal Wysocki; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2017)

2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. - Szymon Reszewicz; Krzysztof Siwiec; Witold A. Pleskacz (DDECS, 2018)

Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology. - Igor Butryn; Lukasz Wiechowski; Daniel Pietron; Witold A. Pleskacz (MIXDES, 2018)

Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology. - Daniel Pietron; Igor Butryn; Lukasz Wiechowski; Witold A. Pleskacz (MIXDES, 2018)

Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). - Zoran Stamenkovic; Ondrej Novák; Witold A. Pleskacz (Microelectron. Reliab., 2018)

Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. - Mariusz Derlecki; Krzysztof Siwiec; Pawel Narczyk; Witold A. Pleskacz (DDECS, 2019)

International Symposium on Design and Diagnostics of Electronic Circuits and Systems. - Zoran Stamenkovic; Alberto Bosio; György Cserey; Ondrej Novák; Witold A. Pleskacz; Lukás Sekanina; Andreas Steininger; Goran Stojanovic; Viera Stopjaková (ITC, 2019)

DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology. - Adam Borkowski; Tomasz Borejko; Witold A. Pleskacz (MIXDES, 2019)

Retargeting the MIPS-II CPU Core to the RISC-V Architecture. - Sebastian Cieslak; Adrian Oleksiak; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)

Design and Verification Environment for RISC-V Processor Cores. - Adrian Oleksiak; Sebastian Cieslak; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)

Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication. - Lukasz Ostrowski; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)

Configurable MBIST Processor for Embedded Memories Testing. - Andrzej A. Wojciechowski; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)

CMOS Differential Amplifier as a Physically Unclonable Function. - Szymon Reszewicz; Krzysztof Siwiec; Witold A. Pleskacz (DDECS, 2020)

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. - Tomasz Borejko; Krzysztof Marcinek; Krzysztof Siwiec; Pawel Narczyk; Adam Borkowski; Igor Butryn; Arkadiusz W. Luczyk; Daniel Pietron; Maciej Plasota; Szymon Reszewicz; Lukasz Wiechowski; Witold A. Pleskacz (Sensors, 2020)

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. - Tomasz Borejko; Krzysztof Marcinek; Krzysztof Siwiec; Pawel Narczyk; Adam Borkowski; Igor Butryn; Arkadiusz W. Luczyk; Daniel Pietron; Maciej Plasota; Szymon Reszewicz; Lukasz Wiechowski; Witold A. Pleskacz (Sensors, 2020)

GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing. - Krzysztof Marcinek; Witold A. Pleskacz (Sensors, 2020)

Class AB Operational Amplifier in CMOS 55 nm Technology. - Pawel Pienczuk; Witold A. Pleskacz; Mateusz Teodorowski (MIXDES, 2021)

DC/DC Buck Converter Soft-Start Methods. - Adam Borkowski; Krzysztof Siwiec; Witold A. Pleskacz (MIXDES, 2022)

Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits. - Andrzej A. Wojciechowski; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2022)

Dual TDL Based Phase Difference Detector Architecture. - Andrzej A. Wojciechowski; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2023)

The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. - Marika Grochowska; Witold A. Pleskacz (DDECS, 2024)

Bridge Circuit Converting Atomic Transactions Between AMBA AXI4 and AMBA AXI5 Standards. - Jakub Misztal; Mateusz Korona; Witold A. Pleskacz (MIXDES, 2024)

Implementation of Hardware Trace Buffer Module for RISC-V Processor Core. - Bohdan Shveida; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2024)