Statistical Simulation of the IC Manufacturing Process. - Wojciech Maly; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982)

Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. - Wojciech Maly; F. Joel Ferguson; John Paul Shen (ITC, 1984)

Inductive Fault Analysis of MOS Integrated Circuits. - John Paul Shen; Wojciech Maly; F. Joel Ferguson (IEEE Des. Test, 1985)

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. - Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Tolerance Assignment for IC Selection Tests. - Wojciech Maly; Zygmunt Pizlo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Optimal order of the VLSI IC testing sequence. - Wojciech Maly (DAC, 1986)

VLSI Yield Prediction and Estimation: A Unified Framework. - Wojciech Maly; Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

Realistic Fault Modeling for VLSI Testing. - Wojciech Maly (DAC, 1987)

Built-in current testing-feasibility study. - Wojciech Maly; Phil Nigh (ICCAD, 1988)

Testing oriented analysis of CMOS ICs with opens. - Wojciech Maly; Pranab K. Nag; Phil Nigh (ICCAD, 1988)

Current sensing for built-in testing of CMOS circuits. - Derek B. I. Feltham; Phil Nigh; L. Richard Carley; Wojciech Maly (ICCD, 1988)

Layout-driven test generation. - Phil Nigh; Wojciech Maly (ICCAD, 1989)

Process Monitoring Oriented IC Testing. - Wojciech Maly; Samir B. Naik (ITC, 1989)

Current testing. - Wojciech Maly (ITC, 1990)

CMOS bridging fault detection. - Thomas M. Storey; Wojciech Maly (ITC, 1990)

Test Generation for Current Testing (CMOS ICs). - Phil Nigh; Wojciech Maly (IEEE Des. Test Comput., 1990)

Computer-aided design for VLSI circuit manufacturability. - Wojciech Maly (Proc. IEEE, 1990)

What is Design for Manufacturability (DFM)? (Panel Abstract). - Wojciech Maly (DAC, 1991)

Improving the Quality of Test Education. - Wojciech Maly (ITC, 1991)

Fault Modeling for the Testing of Mixed Integrated Circuits. - Anne Meixner; Wojciech Maly (ITC, 1991)

Stuck Fault and Current Testing Comparison Using CMOS Chip Test. - Thomas M. Storey; Wojciech Maly; John Andrews; Myron Miske (ITC, 1991)

Physically realistic fault models for analog CMOS neural networks. - Derek B. I. Feltham; Wojciech Maly (IEEE J. Solid State Circuits, 1991)

Design for testability view on placement and routing. - Derek B. I. Feltham; Jitendra Khare; Wojciech Maly (EURO-DAC, 1992)

Prospects for WSI: A Manufacturing Perspective. - Wojciech Maly (Computer, 1992)

Design of ICs applying built-in current testing. - Wojciech Maly; Marek J. Patyra (J. Electron. Test., 1992)

Built-in current testing. - Wojciech Maly; Marek J. Patyra (IEEE J. Solid State Circuits, 1992)

Estimation of reject ratio in testing of combinatorial circuits. - Dinesh D. Gaitonde; Jitendra Khare; D. M. H. Walker; Wojciech P. Maly (VTS, 1993)

Computer-aided failure analysis of VLSI circuits using IDDQ testing. - Samir B. Naik; Wojciech P. Maly (VTS, 1993)

Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. - Samir Naik; Frank Agricola; Wojciech Maly (IEEE Des. Test Comput., 1993)

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. - Jitendra Khare; Derek B. I. Feltham; Wojciech Maly (IEEE J. Solid State Circuits, 1993)

Cost of Silicon Viewed from VLSI Design Perspective. - Wojciech Maly (DAC, 1994)

Feasibility Study of Smart Substrate Multichip Modules. - Anne E. Gattiker; Wojciech Maly (ITC, 1994)

Integration of Design, Manufacturing and Testing. - Wojciech Maly (ITC, 1994)

Smart-Substrate Multichip-Module Systems. - Wojciech Maly; Derek B. I. Feltham; Anne E. Gattiker; Mark D. Hobaugh; Kenneth Backus; Michael E. Thomas (IEEE Des. Test Comput., 1994)

On Test Set Preservation of Retimed Circuits. - Aiman H. El-Maleh; Thomas E. Marchok; Janusz Rajski; Wojciech Maly (DAC, 1995)

Complexity of sequential ATPG. - Thomas E. Marchok; Aiman El-Maleh; Wojciech Maly; Janusz Rajski (ED&TC, 1995)

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. - Igor Bubel; Wojciech Maly; Thomas Waas; Pranab K. Nag; Hans Hartmann; Doris Schmitt-Landsiedel; Susanne Griep (DFT, 1995)

Accurate yield estimation of circuits with redundancy. - Dinesh D. Gaitonde; D. M. H. Walker; Wojciech Maly (DFT, 1995)

Hierarchical extraction of critical area for shorts in very large ICs. - Pranab K. Nag; Wojciech Maly (DFT, 1995)

Inductive Contamination Analysis (ICA) with SRAM Application. - Jitendra Khare; Wojciech Maly (ITC, 1995)

Testability Implications of Performance-Driven Logic Synthesis. - Thomas E. Marchok; Aiman H. El-Maleh; Janusz Rajski; Wojciech Maly (IEEE Des. Test Comput., 1995)

Iddq Testing for High Performance CMOS - The Next Ten Years. - Thomas W. Williams; Rohit Kapur; M. Ray Mercer; Robert H. Dennard; Wojciech Maly (ED&TC, 1996)

Fatal Fault Probability Prediction for Array Based Designs. - Dinesh D. Gaitonde; Wojciech Maly; D. M. H. Walker (DFT, 1996)

Detection of an antenna effect in VLSI designs. - Wojciech Maly; Charles H. Ouyang; Subhendra Ghosh; Sury Maturi (DFT, 1996)

Extraction of critical areas for opens in large VLSI circuits. - Charles H. Ouyang; Witold A. Pleskacz; Wojciech Maly (DFT, 1996)

Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. - Hans T. Heineken; Wojciech Maly (ICCAD, 1996)

Design for manufacturability in submicron domain. - Wojciech Maly; Hans T. Heineken; Jitendra Khare; Pranab K. Nag (ICCAD, 1996)

Modeling the Difficulty of Sequential Automatic Test Pattern Generation. - Thomas E. Marchok; Wojciech Maly (ICCD, 1996)

New and Not-So-New Test Challenges of the Next Decade. - Wojciech Maly (ITC, 1996)

IDDQ Test: Sensitivity Analysis of Scaling. - Thomas W. Williams; Robert H. Dennard; Rohit Kapur; M. Ray Mercer; Wojciech Maly (ITC, 1996)

Can Defect-Tolerant Chips Better Meet the Quality Challenge? - R. L. Campbell; P. Kuekes; David Y. Lepejian; Wojciech P. Maly; Michael Nicolaidis; Alex Orailoglu (VTS, 1996)

Current signatures [VLSI circuit testing]. - Anne E. Gattiker; Wojciech Maly (VTS, 1996)

Fault characterization of standard cell libraries using inductive contamination. - Jitendra Khare; Wojciech Maly; Nathan Tiday (VTS, 1996)

The future of IC design, testing, and manufacturing. - Wojciech Maly (IEEE Des. Test Comput., 1996)

A complexity analysis of sequential ATPG. - Thomas E. Marchok; Aiman H. El-Maleh; Wojciech Maly; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

CAD at the Design-Manufacturing Interface. - Hans T. Heineken; Jitendra Khare; Wojciech Maly; Pranab K. Nag; Charles H. Ouyang; Witold A. Pleskacz (DAC, 1997)

Improved Yield Model for Submicron Domain. - Witold A. Pleskacz; Wojciech Maly (DFT, 1997)

Detection of Yield Trends. - Witold A. Pleskacz; Wojciech Maly; Hans T. Heineken (DFT, 1997)

Current Signatures: Application. - Anne E. Gattiker; Wojciech Maly (ITC, 1997)

So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. - Phil Nigh; Wayne M. Needham; Kenneth M. Butler; Peter C. Maxwell; Robert C. Aitken; Wojciech Maly (ITC, 1997)

To DFT or Not to DFT? - Sichao Wei; Pranab K. Nag; Ronald D. Blanton; Anne E. Gattiker; Wojciech Maly (ITC, 1997)

Smart Substrate MCMs. - Anne E. Gattiker; Wojciech Maly (J. Electron. Test., 1997)

Behavior and testability preservation under the retiming transformation. - Aiman H. El-Maleh; Thomas E. Marchok; Janusz Rajski; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Performance - Manufacturability Tradeoffs in IC Design. - Hans T. Heineken; Wojciech Maly (DATE, 1998)

Design-Manufacturing Interface: Part I - Vision. - Wojciech Maly; Pranab K. Nag; Hans T. Heineken; Jitendra Khare (DATE, 1998)

Design-Manufacturing Interface: Part II - Applications. - Wojciech Maly; Pranab K. Nag; Charles H. Ouyang; Hans T. Heineken; Jitendra Khare; P. Simon (DATE, 1998)

Moore's law and physical design of ICs. - Wojciech Maly (ISPD, 1998)

A pattern matching algorithm for verification and analysis of very large IC layouts. - Mariusz Niewczas; Wojciech Maly; Andrzej J. Strojwas (ISPD, 1998)

Current signatures: application [to CMOS]. - Anne E. Gattiker; Wojciech Maly (ITC, 1998)

Toward understanding "Iddq-only" fails. - Anne E. Gattiker; Wojciech Maly (ITC, 1998)

An algorithm for determining repetitive patterns in very large IC layouts. - Mariusz Niewczas; Wojciech Maly; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. - Witold A. Pleskacz; Charles H. Ouyang; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Cost based tradeoff analysis of standard cell designs. - Peng Li 001; Pranab K. Nag; Wojciech Maly (SLIP, 2000)

IC Design in High-Cost Nanometer-Technologies Era. - Wojciech Maly (DAC, 2001)

Interconnect characteristics of 2.5-D system integration scheme. - Yangdong Deng; Wojciech Maly (ISPD, 2001)

Quality of Design from an IC Manufacturing Perspective. - Wojciech Maly (ISQED, 2001)

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. - John T. Chen; Jitendra Khare; Ken Walker; Saghir A. Shaikh; Janusz Rajski; Wojciech Maly (ITC, 2001)

Enabling Embedded Memory Diagnosis via Test Response Compression. - John T. Chen; Wojciech Maly; Janusz Rajski; Omar Kebichi; Jitendra Khare (VTS, 2001)

Limitations and challenges of computer-aided design technology for CMOS VLSI. - Randal E. Bryant; Kwang-Ting Cheng; Andrew B. Kahng; Kurt Keutzer; Wojciech Maly; A. Richard Newton; Lawrence T. Pileggi; Jan M. Rabaey; Alberto L. Sangiovanni-Vincentelli (Proc. IEEE, 2001)

Fault Tuples in Diagnosis of Deep-Submicron Circuits. - Ronald D. Blanton; John T. Chen; Rao Desineni; Kumar N. Dwarakanath; Wojciech Maly; Thomas J. Vogels (ITC, 2002)

Modeling the Economics of Testing: A DFT Perspective. - Pranab K. Nag; Anne E. Gattiker; Sichao Wei; Ronald D. Blanton; Wojciech Maly (IEEE Des. Test Comput., 2002)

Physical Design of the "2.5D" Stacked System. - Yangdong Deng; Wojciech Maly (ICCD, 2003)

Deformations of IC Structure in Test and Yield Learning. - Wojciech Maly; Anne E. Gattiker; Thomas Zanon; Thomas J. Vogels; R. D. (Shawn) Blanton; Thomas M. Storey (ITC, 2003)

Progressive Bridge Identification. - Thomas J. Vogels; Wojciech Maly; R. D. (Shawn) Blanton (ITC, 2003)

2.5D system integration: a design driven system implementation schema. - Yangdong Steve Deng; Wojciech Maly (ASP-DAC, 2004)

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. - Thomas J. Vogels; Thomas Zanon; Rao Desineni; R. D. (Shawn) Blanton; Wojciech Maly; Jason G. Brown; Jeffrey E. Nelson; Y. Fei; X. Huang; Padmini Gopalakrishnan; Mahim Mishra; Vyacheslav Rovner; et al. (ITC, 2004)

2.5-dimensional VLSI system integration. - Yangdong Deng; Wojciech P. Maly (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Extraction of defect density and size distributions from wafer sort test results. - Jeffrey E. Nelson; Thomas Zanon; Rao Desineni; Jason G. Brown; N. Patil; Wojciech Maly; R. D. (Shawn) Blanton (DATE, 2006)

Extracting Defect Density and Size Distributions from Product ICs. - Jeffrey E. Nelson; Thomas Zanon; Jason G. Brown; Osei Poku; R. D. (Shawn) Blanton; Wojciech Maly; Brady Benware; Chris Schuermyer (IEEE Des. Test Comput., 2006)

OPC-Free and Minimally Irregular IC Design Style. - Wojciech Maly; Yi-Wei Lin; Malgorzata Marek-Sadowska (DAC, 2007)

More Moore: foolish, feasible, or fundamentally different? - Rob Aitken; Jerry Bautista; Wojciech Maly; Jan M. Rabaey (ICCAD, 2008)

Is there always performance overhead for regular fabric? - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly; Andrzej Pfitzner; Dominik Kasprowicz (ICCD, 2008)

Adder Circuits with Transistors using Independently Controlled Gates. - Marcus Weis; Andrzej Pfitzner; Dominik Kasprowicz; Rainer Emling; Wojciech Maly; Doris Schmitt-Landsiedel (ISCAS, 2009)

Transistor-level layout of high-density regular circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2009)

Vertical slit transistor based integrated circuits (VeSTICs) paradigm. - Wojciech Maly (ISPD, 2009)

Performance study of VeSFET-based, high-density regular circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2010)

Evaluating yield and testing impact of sub-wavelength lithography. - Wing Chiu Tam; R. D. (Shawn) Blanton; Wojciech Maly (VTS, 2010)

Layout Generator for Transistor-Level High-Density Regular Circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Vertical slit transistor based integrated circuits (veSTICs): feasibility study. - Wojciech Maly (ISPD, 2011)

On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Vertical Slit Field Effect Transistor in ultra-low power applications. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech Maly (ISQED, 2012)

Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech Maly (ISPD, 2013)

Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech P. Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. - Xiang Qiu; Malgorzata Marek-Sadowska; Wojciech P. Maly (IEEE Trans. Very Large Scale Integr. Syst., 2015)