Towards a common RT-level subset of VHDL. - Wolfgang Ecker (EURO-DAC, 1992)

The design cube: a new model for VHDL designflow representation. - Wolfgang Ecker; Michael Hofmeister (EURO-DAC, 1992)

Subtype concept of VHDL for synthesis constraints. - Wolfgang Ecker; Sabine März (EURO-DAC, 1992)

System-Level Specification and Design Using VHDL: A Case Study. - Wolfgang Ecker; Sabine März (CHDL, 1993)

Using VHDL for HW/SW co-specification. - Wolfgang Ecker (EURO-DAC, 1993)

State look ahead technique for cycle optimization of interacting finite state Moore machines. - Wolfgang Ecker; Michael Hofmeister (ICCAD, 1993)

Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. - Wolfgang Ecker; Manfred Glesner; Andreas Vombach (EURO-DAC, 1994)

Semi-dynamic scheduling of synchronization-mechanisms. - Wolfgang Ecker (EURO-DAC, 1995)

A classification of design steps and their verification. - Wolfgang Ecker (EURO-DAC, 1995)

VHDL-based communication and synchronization synthesis. - Wolfgang Ecker; Manfred Huber (EURO-DAC, 1995)

Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. - Claus Schneider; Wolfgang Ecker (EURO-DAC, 1996)

Verification methods for VHDL RTL-subroutines. - Wolfgang Ecker (J. Syst. Archit., 1996)

VHDL synthesis description portability: The need for Level synthesis subsets. - Manfred Selz; Wolfgang Ecker; Eugenio Villar (J. Syst. Archit., 1996)

Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. - Matthias Bauer 003; Wolfgang Ecker (DAC, 1997)

The Shall-Prototype-Test Development model. - Michael Mrva; Mike Heuchling; Wolfgang Ecker (ECBS, 1997)

Reuse-Potentiale im Hardware-Entwurf. - Wolfgang Ecker; Yvonne Fritzsch; Viktor Preis (Informationstechnik Tech. Inform., 1998)

A Method for Accelerating Test Environments. - Matthias Bauer 003; Wolfgang Ecker; Renate Henftling; Andreas Zinn (EUROMICRO, 1999)

A scalable multithreaded compiler front-end. - André Windisch; Thomas Schneider 006; Ke Yang; Jochen Mades; Wolfgang Ecker (PARCO, 1999)

An Open VHDL-AMS Simulation Framework. - Thomas Schneider 006; Jochen Mades; Manfred Glesner; André Windisch; Wolfgang Ecker (BMAS, 2000)

Graphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML. - Matthias Bauer 003; Wolfgang Ecker; Andreas Zinn (MBMV, 2000)

VXML: VHDL Hardware Design Representation in XML. - Wolfgang Ecker; Mike Heuchling; Jochen Mades; Thomas Schneider 006; André Windisch; Ke Yang (MBMV, 2000)

A JAVA-Based Mixed-Signal Design Environment. - Jochen Mades; Thomas Schneider 006; Manfred Glesner; André Windisch; Wolfgang Ecker (SBCCI, 2000)

Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). - André Windisch; Thomas Schneider 006; Jochen Mades; Dieter Monjau; Manfred Glesner; Carsten Hammer; Wolfgang Ecker (Informationstechnik Tech. Inform., 2000)

Hardware-basierter Hardware-Entwurf. - Wolfgang Ecker (MBMV (1), 2001)

Verifikation und Wiederverwendung (Verification and Re-Use). - Matthias Bauer 003; Wolfgang Ecker; Renate Henftling; Martin Zambaldi; Andreas Zinn (Informationstechnik Tech. Inform., 2002)

Re-use-centric architecture for a fully accelerated testbench environment. - Renate Henftling; Andreas Zinn; Matthias Bauer 003; Martin Zambaldi; Wolfgang Ecker (DAC, 2003)

Platform-Based Testbench Generation. - Renate Henftling; Andreas Zinn; Matthias Bauer 003; Wolfgang Ecker; Martin Zambaldi (DATE, 2003)

An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. - Renate Henftling; Wolfgang Ecker; Andreas Zinn; Martin Zambaldi; Matthias Bauer 003 (IPDPS, 2003)

Incremental Design: A VHDL based Case Study. - Fanny Garnier; Wolfgang Ecker (MBMV, 2003)

An Enhanced Environment for Multi-Level Simulation. - Martin Zambaldi; Matthias Bauer 003; Wolfgang Ecker; Renate Henftling; Andreas Zinn (MBMV, 2003)

SystemVerilog: Interface Based Design. - Peter Jensen; Wolfgang Ecker; Thomas Kruse; Martin Zambaldi (FDL, 2004)

Extending the RASSP model for Verification. - Martin Zambaldi; Wolfgang Ecker (FDL, 2004)

The Formal Simulation Semantics of SystemVerilog. - Martin Zambaldi; Wolfgang Ecker; Thomas Kruse; Wolfgang Müller 003 (FDL, 2004)

Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Martin Zambaldi (ISORC, 2004)

How to Bridge the Gap Between Simulationand Test. - Martin Zambaldi; Wolfgang Ecker (ITC, 2004)

Ein orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen. - Martin Zambaldi; Wolfgang Ecker (MBMV, 2004)

A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. - Martin Zambaldi; Wolfgang Ecker; Renate Henftling; Matthias Bauer 003 (IEEE Des. Test Comput., 2004)

Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. - Wolfgang Ecker; Lothar Schrader (GI Jahrestagung (1), 2005)

Case Study on Transaction Level Modeling. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten (FDL, 2006)

IP Library For Temporal SystemC Assertions. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Jacob Smit (FDL, 2006)

Specification Language for Transaction Level Assertions. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Michael Hull (HLDVT, 2006)

Requirements and Concepts for Transaction Level Assertions. - Wolfgang Ecker; Volkan Esen; Michael Hull; Thomas Steininger; Michael Velten (ICCD, 2006)

Execution semantics and formalisms for multi-abstraction TLM assertions. - Wolfgang Ecker; Volkan Esen; Michael Hull (MEMOCODE, 2006)

Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. - Wolfgang Ecker; Volkan Esen; Lars Schönberg; Thomas Steininger; Michael Velten; Michael Hull (DATE, 2007)

Interactive presentation: Implementation of a transaction level assertion framework in SystemC. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Michael Hull (DATE, 2007)

Requirements and Concepts for Transaction Level Assertion Refinement. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten (IESS, 2007)

Industrial IP Integration Flows based on IP-XACT Standards. - Wido Kruijtzer; Pieter van der Wolf; Erwin A. de Kock; Jan Stuyt; Wolfgang Ecker; Albrecht Mayer; Serge Hustin; Christophe Amerijckx; Serge de Paoli; Emmanuel Vaumorin (DATE, 2008)

Using a dataflow abstracted virtual prototype for HdS-design. - Wolfgang Ecker; Stefan Heinen; Michael Velten (ASP-DAC, 2009)

Panel Session - Who Is Closing the embedded software design gap? - Wolfgang Ecker; Pierre Bricaud; Rainer Dömer; Yossi Veller; Stefan Heinen; Jürgen Mössinger; Andreas von Schwerin (DATE, 2010)

TLM+ modeling of embedded HW/SW systems. - Wolfgang Ecker; Volkan Esen; Robert Schwencker; Thomas Steininger; Michael Velten (DATE, 2010)

Model reduction techniques for the formal verification of hardware dependent software. - Wolfgang Ecker; Volkan Esen; Rainer Findenig; Thomas Steininger; Michael Velten (HLDVT, 2010)

Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. - Rainer Findenig; Thomas Leitner; Michael Velten; Wolfgang Ecker (HLDVT, 2010)

State chart refinement validation from approximately timed to cycle callable models. - Rainer Findenig; Wolfgang Ecker (SoC, 2010)

Analog transaction level modeling. - Alexander W. Rath; Volkan Esen; Wolfgang Ecker (HLDVT, 2011)

SystemC as completing pillar in industrial OVM based verification environments. - Wolfgang Ecker; Volkan Esen; Michael Velten; Tudor Timisescu (CODES+ISSS, 2012)

Testbenches for advanced TLM verification. - Wolfgang Müller 003; Wolfgang Ecker (CODES+ISSS, 2012)

The system verification methodology for advanced TLM verification. - Marcio Ferreira da Silva Oliveira; Christoph Kuznik; Hoang Minh Le 001; Daniel Große; Finn Haedicke; Wolfgang Müller 003; Rolf Drechsler; Wolfgang Ecker; Volkan Esen (CODES+ISSS, 2012)

Single-source hardware modeling of different abstraction levels with State Charts. - Rainer Findenig; Thomas Leitner; Wolfgang Ecker (HLDVT, 2012)

Transaction-Level Modeling and Refinement Using State Charts. - Rainer Findenig; Thomas Leitner; Wolfgang Ecker (EUROCAST (1), 2013)

Comparison of analog transactions using statistics. - Alexander W. Rath; Volkan Esen; Wolfgang Ecker (ISSoC, 2013)

The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. - Juergen Karmann; Wolfgang Ecker (PATMOS, 2013)

A transaction-oriented UVM-based library for verification of analog behavior. - Alexander W. Rath; Volkan Esen; Wolfgang Ecker (ASP-DAC, 2014)

Metasynthesis for Designing Automotive SoCs. - Wolfgang Ecker; Michael Velten; Leily Zafari; Ajay Goyal (DAC, 2014)

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. - Jan-Hendrik Oetjens; Nico Bannow; Markus Becker 001; Oliver Bringmann 001; Andreas Burger; Moomen Chaari; Samarjit Chakraborty; Rolf Drechsler; Wolfgang Ecker; Kim Grüttner; Thomas Kruse; Christoph Kuznik; et al. (DAC, 2014)

The metamodeling approach to system level synthesis. - Wolfgang Ecker; Michael Velten; Leily Zafari; Ajay Goyal (DATE, 2014)

A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. - Moomen Chaari; Wolfgang Ecker; Cristiano Novello; Bogdan-Andrei Tabacaru; Thomas Kruse (DAC, 2015)

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. - Oliver Bringmann 001; Wolfgang Ecker; Andreas Gerstlauer; Ajay Goyal; Daniel Mueller-Gritschneder; Prasanth Sasidharan; Simranjit Singh (DATE, 2015)

Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation. - Bogdan-Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello (DSD, 2016)

Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes. - Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello; Bogdan-Andrei Tabacaru (DSN Workshops, 2016)

Fault-effect analysis on system-level hardware modeling using virtual prototypes. - Bogdan-Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello (FDL, 2016)

Design centric modeling of digital hardware. - Johannes Schreiner; Rainer Findenig; Wolfgang Ecker (HLDVT, 2016)

Where formal verification can help in functional safety analysis. - Alessandro Bernardini; Wolfgang Ecker; Ulf Schlichtmann (ICCAD, 2016)

Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. - Bogdan-Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello (SAFECOMP Workshops, 2016)

Efficient handling of the fault space in functional safety analysis utilizing formal methods. - Alessandro Bernardini; Wolfgang Ecker; Ulf Schlichtmann (VLSI-SoC, 2016)

Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. - Wolfgang Ecker; Johannes Schreiner (VLSI-SoC, 2016)

Automatically comparing analog behavior using Earth Mover's Distance. - Alexander W. Rath; Sebastian Simon; Volkan Esen; Wolfgang Ecker (VLSI-SoC, 2016)

Earth Mover's Distance as a Comparison Metric for Analog Behavior. - Alexander W. Rath; Sebastian Simon; Volkan Esen; Wolfgang Ecker (VLSI-SoC (Selected Papers), 2016)

Digital Hardware Design Based on Metamodels and Model Transformations. - Johannes Schreiner; Wolfgang Ecker (VLSI-SoC (Selected Papers), 2016)

Speeding up safety verification by fault abstraction and simulation to transaction level. - Bogdan-Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello (VLSI-SoC, 2016)

On generation of properties from specification. - Keerthikumara Devarajegowda; Wolfgang Ecker (HLDVT, 2017)

Python based framework for HDSLs with an underlying formal semantics: (Invited paper). - Keerthikumara Devarajegowda; Johannes Schreiner; Rainer Findenig; Wolfgang Ecker (ICCAD, 2017)

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. - Daniel Mueller-Gritschneder; Keerthikumara Devarajegowda; Martin Dittrich; Wolfgang Ecker; Marc Greim; Ulf Schlichtmann (RSP, 2017)

Metamodeling and Code Generation in the Hardware/Software Interface Domain. - Wolfgang Ecker; Johannes Schreiner (Handbook of Hardware/Software Codesign, 2017)

A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. - Elena Zennaro; Lorenzo Servadei; Keerthikumara Devarajegowda; Wolfgang Ecker (DSD, 2018)

Analog fault simulation automation at schematic level with random sampling techniques. - Liang Wu; Mohammad Khizer Hussain; Saed Abughannam; Wolfgang Müller 003; Christoph Scheytt; Wolfgang Ecker (DTIS, 2018)

Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. - Lorenzo Servadei; Elena Zennaro; Keerthikumara Devarajegowda; Wolfgang Ecker; Robert Wille (CIMA@ICTAI, 2018)

Meta-model Based Automation of Properties for Pre-Silicon Verification. - Keerthikumara Devarajegowda; Wolfgang Ecker (VLSI-SoC, 2018)

Increasing Soft Error Resilience by Software Transformation. - Michael Werner; Keerthikumara Devarajegowda; Moomen Chaari; Wolfgang Ecker (DAC, 2019)

Embedded Systems' Automation following OMG's Model Driven Architecture Vision. - Wolfgang Ecker; Keerthikumara Devarajegowda; Michael Werner; Zhao Han; Lorenzo Servadei (DATE, 2019)

Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. - Lorenzo Servadei; Elena Zennaro; Keerthikumara Devarajegowda; Martin Manzinger; Wolfgang Ecker; Robert Wille (DATE, 2019)

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. - Eshan Singh; Keerthikumara Devarajegowda; Sebastian Simon; Ralf Schnieder; Karthik Ganesan 001; Mohammad Rahmani Fadiheh; Dominik Stoffel; Wolfgang Kunz; Clark W. Barrett; Wolfgang Ecker; Subhasish Mitra (DATE, 2019)

Formal Verification Methodology in an Industrial Setup. - Lorenzo Servadei; Zhao Han; Michael Werner; Wolfgang Ecker; Keerthikumara Devarajegowda (DSD, 2019)

How to Keep 4-Eyes Principle in a Design and Property Generation Flow. - Keerthikumara Devarajegowda; Wolfgang Ecker; Wolfgang Kunz (MBMV, 2019)

Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. - Zhao Han; Keerthikumara Devarajegowda; Michael Werner; Wolfgang Ecker (NORCAS, 2019)

Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. - Lorenzo Servadei; Elena Zennaro; Tobias Fritz; Keerthikumara Devarajegowda; Wolfgang Ecker; Robert Wille (Microprocess. Microsystems, 2019)

Gap-free Processor Verification by S2QED and Property Generation. - Keerthikumara Devarajegowda; Mohammad Rahmani Fadiheh; Eshan Singh; Clark W. Barrett; Subhasish Mitra; Wolfgang Ecker; Dominik Stoffel; Wolfgang Kunz (DATE, 2020)

Kamel: IP-XACT compatible intermediate meta-model for IP generation. - Antti Rautakoura; Matti Käyrä; Timo D. Hämäläinen; Wolfgang Ecker; Esko Pekkarinen; Mikko Teuho (DSD, 2020)

Optimized HW/FW Generation from an Abstract Register Interface Model. - Michael Werner; Igli Zeraliu; Zhao Han; Sebastian Siegfried Prebeck; Lorenzo Servadei; Wolfgang Ecker (DSD, 2020)

Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. - Lorenzo Servadei; Edoardo Mosca; Keerthikumara Devarajegowda; Michael Werner; Wolfgang Ecker; Robert Wille (ACM Great Lakes Symposium on VLSI, 2020)

SoC Design Automation with ML - It's Time for Research. - Vijay Deep Bhatt; Wolfgang Ecker; Volkan Esen; Zhao Han; Daniela Sanchez Lopera; Rituj Patel; Lorenzo Servadei; Sahil Singla 003; Sven Wenzek; Vijaydeep Yadav; Elena Zennaro (MLCAD, 2020)

Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning. - Lorenzo Servadei; Jiapeng Zheng; Jose A. Arjona-Medina; Michael Werner; Volkan Esen; Sepp Hochreiter; Wolfgang Ecker; Robert Wille (MLCAD, 2020)

Automatic compiler optimization on embedded software through k-means clustering. - Michael Werner; Lorenzo Servadei; Robert Wille; Wolfgang Ecker (MLCAD, 2020)

Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. - Lorenzo Servadei; Edoardo Mosca; Elena Zennaro; Keerthikumara Devarajegowda; Michael Werner; Wolfgang Ecker; Robert Wille (IEEE Trans. Computers, 2020)

Automated HW/SW co-design for edge AI: state, challenges and steps ahead. - Oliver Bringmann 001; Wolfgang Ecker; Ingo Feldner; Adrian Frischknecht; Christoph Gerum; Timo Hämäläinen 001; Muhammad Abdullah Hanif; Michael J. Klaiber; Daniel Mueller-Gritschneder; Paul Palomero Bernardo; Sebastian Siegfried Prebeck; Muhammad Shafique 001 (CODES+ISSS, 2021)

ISA Modeling with Trace Notation for Context Free Property Generation. - Keerthikumara Devarajegowda; Endri Kaja; Sebastian Siegfried Prebeck; Wolfgang Ecker (DAC, 2021)

Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. - Endri Kaja; Nicolas Gerlin; Mounika Vaddeboina; Luis Rivas; Sebastian Siegfried Prebeck; Zhao Han; Keerthikumara Devarajegowda; Wolfgang Ecker (DFT, 2021)

On Self-Verifying DSL Generation for Embedded Systems Automation. - Zhao Han; Shahzaib Qazi; Michael Werner; Keerthikumara Devarajegowda; Wolfgang Ecker (MBMV, 2021)

Extending Verilator to Enable Fault Simulation. - Endri Kaja; Nicolas Ojeda Leon; Michael Werner; Bogdan-Andrei Tabacaru; Keerthikumara Devarajegowda; Wolfgang Ecker (MBMV, 2021)

A Survey of Graph Neural Networks for Electronic Design Automation. - Daniela Sanchez Lopera; Lorenzo Servadei; Gamze Naz Kiprit; Souvik Hazra; Robert Wille; Wolfgang Ecker (MLCAD, 2021)

RTL Delay Prediction Using Neural Networks. - Daniela Sanchez Lopera; Lorenzo Servadei; Vishwa Priyanka Kasi; Sebastian Siegfried Prebeck; Wolfgang Ecker (NorCAS, 2021)

Transformative Hardware Design Following the Model-Driven Architecture Vision. - Zhao Han; Gabriel Rutsch; Deyan Wang; Bowen Li; Sebastian Siegfried Prebeck; Daniela Sanchez Lopera; Keerthikumara Devarajegowda; Wolfgang Ecker (VLSI-SoC (Selected Papers), 2021)

Aspect-Oriented Design Automation with Model Transformation. - Zhao Han; Deyan Wang; Gabriel Rutsch; Bowen Li; Sebastian Siegfried Prebeck; Daniela Sanchez Lopera; Keerthikumara Devarajegowda; Wolfgang Ecker (VLSI-SoC, 2021)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)

MetaFS: Model-driven Fault Simulation Framework. - Endri Kaja; Nicolas Gerlin; Monideep Bora; Keerthikumara Devarajegowda; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (DFT, 2022)

Applying GNNs to Timing Estimation at RTL. - Daniela Sanchez Lopera; Wolfgang Ecker (ICCAD, 2022)

A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. - Sebastian Prebeck; Sathya Ashok; Mounika Vaddeboina; Keerthikumara Devarajegowda; Wolfgang Ecker (MBMV, 2022)

Industrial Experience with Open-Source EDA Tools. - Christian Lück; Daniela Sanchez Lopera; Sven Wenzek; Wolfgang Ecker (MLCAD, 2022)

A framework that enables systematic analysis of mixed-signal applications on FPGA. - Gabriel Rutsch; Maximilian Groebner; Anthony Sanders; Konrad Maier; Wolfgang Ecker (RSP, 2022)

A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions. - Sebastian Siegfried Prebeck; Wafic Lawand; Mounika Vaddeboina; Wolfgang Ecker (SAMOS, 2022)

Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. - Nicolas Gerlin; Endri Kaja; Monideep Bora; Keerthikumara Devarajegowda; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (VLSI-SoC, 2022)

Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. - Endri Kaja; Nicolas Gerlin; Monideep Bora; Gabriel Rutsch; Keerthikumara Devarajegowda; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (VLSI-SoC, 2022)

MetFI: Model-driven Fault Simulation Framework. - Endri Kaja; Nicolas Gerlin; Luis Rivas; Monideep Bora; Keerthikumara Devarajegowda; Wolfgang Ecker (CoRR, 2022)

Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters. - Rana Elnaggar; Lorenzo Servadei; Shubham Mathur; Robert Wille; Wolfgang Ecker; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. - Steven Herbst; Gabriel Rutsch; Wolfgang Ecker; Mark Horowitz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Early RTL delay prediction using neural networks. - Daniela Sanchez Lopera; Lorenzo Servadei; Sebastian Siegfried Prebeck; Wolfgang Ecker (Microprocess. Microsystems, 2022)

Special Session: Machine Learning for Embedded System Design. - Erika S. Alcorta; Andreas Gerstlauer; Chenhui Deng; Qi Sun; Zhiru Zhang; Ceyu Xu; Lisa Wu Wills; Daniela Sanchez Lopera; Wolfgang Ecker; Siddharth Garg; Jiang Hu (CODES+ISSS, 2023)

G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. - Saranyu Chattopadhyay; Keerthikumara Devarajegowda; Bihan Zhao; Florian Lonsing; Brandon A. D'Agostino; Ioanna Vavelidou; Vijay Deep Bhatt; Sebastian Prebeck; Wolfgang Ecker; Caroline Trippel; Clark W. Barrett; Subhasish Mitra (DAC, 2023)

Bits, Flips and RISCs. - Nicolas Gerlin; Endri Kaja; Fabian Vargas 001; Li Lu; Anselm Breitenreiter; Junchao Chen 001; Markus Ulbricht 002; Maribel Gomez; Ares Tahiraga; Sebastian Prebeck; Eyck Jentzsch; Milos Krstic; et al. (DDECS, 2023)

Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications. - Mounika Vaddeboina; Endri Kaja; Alper Yilmayer; Sebastian Prebeck; Wolfgang Ecker (DSD, 2023)

Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. - Johannes Schreiner; Vasundhara Raje Gontia; Sebastian Prebeck; Wolfgang Ecker (MBMV, 2023)

Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. - Endri Kaja; Nicolas Gerlin; Robert Kunzelmann; Keerthikumara Devarajegowda; Wolfgang Ecker (MCSoC, 2023)

Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations. - Daniela Sanchez Lopera; Ishwor Subedi; Wolfgang Ecker (MLCAD, 2023)

Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. - Johannes Kappes; Robert Kunzelmann; Karsten Emrich; Conrad Foik; Daniel Mueller-Gritschneder; Wolfgang Ecker (NorCAS, 2023)

FPGA-Implementation Techniques to Efficiently Test Application Readiness of Mixed-Signal Products. - Gabriel Rutsch; Konrad Maier; Wolfgang Ecker (VLSI-SoC (Selected Papers), 2023)

Deep Reinforcement Learning for Optimization at Early Design Stages. - Lorenzo Servadei; Jin Hwa Lee; José Antonio Arjona-Medina; Michael Werner; Sepp Hochreiter; Wolfgang Ecker; Robert Wille (IEEE Des. Test, 2023)

A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. - Daniela Sánchez; Lorenzo Servadei; Gamze Naz Kiprit; Robert Wille; Wolfgang Ecker (ACM Trans. Design Autom. Electr. Syst., 2023)

A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. - Paul Palomero Bernardo; Patrick Schmid; Oliver Bringmann 001; Mohammed Iftekhar; Babak Sadiye; Wolfgang Mueller; Andreas Koch 001; Eyck Jentzsch; Axel Sauer; Ingo Feldner; Wolfgang Ecker (DATE, 2024)

PaGoRi:A Scalable Parallel Golomb-Rice Decoder. - Mounika Vaddeboina; Endri Kaja; Alper Yilmazer; Uttal Ghosh; Wolfgang Ecker (DDECS, 2024)

An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs. - Endri Kaja; Nicolas Gerlin; Jad Al Halabi; Ares Tahiraga; Sebastian Prebeck; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (DFT, 2024)

Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V. - Endri Kaja; Nicolas Gerlin; Ares Tahiraga; Jad Al Halabi; Sebastian Prebeck; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (DFT, 2024)

Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models. - Mounika Vaddeboina; Alper Yilmayer; Wolfgang Ecker (DSD, 2024)

An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. - Endri Kaja; Nicolas Gerlin; Bihan Zhao; Daniela Sanchez Lopera; Jad Al Halabi; Azam Sher Khan; Sebastian Prebeck; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (ISQED, 2024)

Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. - Daniela Sanchez Lopera; Robert Kunzelmann; Endri Kaja; Wolfgang Ecker (ISQED, 2024)

Leveraging Large Language Models for the Automated Documentation of Hardware Designs. - Saruni Fernando; Robert Kunzelmann; Daniela Sanchez Lopera; Jad Al Halabi; Wolfgang Ecker (MECO, 2024)

Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond. - Mayuri Bhadra; Stephanie Ecker; Daniel Albert; Ravindra Ramaiah; Sebastian Prebeck; Wolfgang Ecker (NorCAS, 2024)

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. - Johannes Schreiner; Daniel Gerl; Robert Kunzelmann; Paritosh Kumar Sinha; Wolfgang Ecker (CoRR, 2024)

Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. - Fatma Jebali; Caaliph Andriamisaina; Mathieu Jan; Wolfgang Ecker; Florian Egert; Bernhard Fischer; Alessio Burrello; Daniele Jahier Pagliari; Sara Vinco; Giuseppe Tagliavini; Ingo Feldner; Andreas Mauderer; et al. (DATE, 2025)

Implementation of Dynamic SISD-SIMD Integer Dividers. - Gianluca Radi; Ares Tahiraga; Robert Kunzelmann; Ties Jan Henderikus Kluter; Wolfgang Ecker (DDECS, 2025)

Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices. - Mounika Vaddeboina; Alper Yilmazer; Wolfgang Ecker (DDECS, 2025)

Moving from RTL- to Handshake-based IP-Design: A RISC-V Case Study. - Natalie Simson; Paritosh Kumar Sinha; Wolfgang Ecker (MECO, 2025)

Execute Your Darlings: Dynamic Execution of High-Level Formal Specifications for Validation and Early Prototyping. - Robert Kunzelmann; Zeyad Tahoun; Wolfgang Ecker (RAPIDO@HiPEAC, 2025)

FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs. - Himanshu Rai; Aishwarya Sridhar; Wolfgang Ecker; Nanditha Rao (VLSID, 2025)