Fast Exact Minimization of BDDs. - Rolf Drechsler; Nicole Drechsler; Wolfgang Günther 001 (DAC, 1998)

Linear Transformations and Exact Minimization of BDDs. - Wolfgang Günther 001; Rolf Drechsler (Great Lakes Symposium on VLSI, 1998)

Using Lower Bounds During Dynamic BDD Minimization. - Rolf Drechsler; Wolfgang Günther 001 (DAC, 1999)

Generation of Optimal Universal Logic Modules. - Rolf Drechsler; Wolfgang Günther 001 (EUROMICRO, 1999)

Efficient Graph Coloring by Evolutionary Algorithms. - Nicole Drechsler; Wolfgang Günther 001; Rolf Drechsler (Fuzzy Days, 1999)

Efficient manipulation algorithms for linearly transformed BDDs. - Wolfgang Günther 001; Rolf Drechsler (ICCAD, 1999)

History-Based Dynamic Minimization During BDD Construction. - Rolf Drechsler; Wolfgang Günther 001 (VLSI, 1999)

Minimization of BDDs using linear transformations based on evolutionary techniques. - Wolfgang Günther 001; Rolf Drechsler (ISCAS (1), 1999)

Creating hard problem instances in logic synthesis using exact minimization. - Wolfgang Günther 001; Rolf Drechsler (ISCAS (6), 1999)

Testability of Circuits Derived from Lattice Diagrams. - Rolf Drechsler; Wolfgang Günther 001; Bernd Becker 001 (EUROMICRO, 2000)

Verification of Designs Containing Black Boxes. - Wolfgang Günther 001; Nicole Drechsler; Rolf Drechsler; Bernd Becker 001 (EUROMICRO, 2000)

k-Layer Straightline Crossing Minimization by Speeding Up Sifting. - Wolfgang Günther 001; Robby Schönfeld; Bernd Becker 001; Paul Molitor (GD, 2000)

Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. - Rolf Drechsler; Wolfgang Günther 001 (GECCO, 2000)

Improving EAs for Sequencing Problems. - Wolfgang Günther 001; Rolf Drechsler (GECCO, 2000)

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. - Wolfgang Günther 001; Rolf Drechsler; Stefan Höreth (ICCD, 2000)

Optimization of sequential verification by history-based dynamic minimization of BDDs. - Rolf Drechsler; Wolfgang Günther 001 (ISCAS, 2000)

Lower Bound Sifting for MDDs. - Dragan Jankovic; Wolfgang Günther 001; Rolf Drechsler (ISMVL, 2000)

Dynamic Re-Encoding During MDD Minimization. - Frank Schmiedle; Wolfgang Günther 001; Rolf Drechsler (ISMVL, 2000)

A Method for Approximate Equivalence Checking. - Mitchell A. Thornton; Rolf Drechsler; Wolfgang Günther 001 (ISMVL, 2000)

On the computational power of linearly transformed BDDs. - Wolfgang Günther 001; Rolf Drechsler (Inf. Process. Lett., 2000)

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. - Wolfgang Günther 001; Rolf Drechsler (J. Syst. Archit., 2000)

Fast exact minimization of BDD's. - Rolf Drechsler; Nicole Drechsler; Wolfgang Günther 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Application of linearly transformed BDDs in sequential verification. - Wolfgang Günther 001; Andreas Hett; Bernd Becker 001 (ASP-DAC, 2001)

Efficient Pattern-Based Verification of Connections to IP Cores . - Ilia Polian; Wolfgang Günther 001; Bernd Becker 001 (Asian Test Symposium, 2001)

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. - Bernd Becker 001; Thomas Eschbach; Rolf Drechsler; Wolfgang Günther 001 (DSD, 2001)

Level Assignment for Displaying Combinational Logic. - Rolf Drechsler; Wolfgang Günther 001; Lothar Linhard; Gerhard Angst (DSD, 2001)

Selection of Efficient Re-Ordering Heuristics for MDD Construction. - Frank Schmiedle; Wolfgang Günther 001; Rolf Drechsler (ISMVL, 2001)

Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. - Ilia Polian; Wolfgang Günther 001; Bernd Becker 001 (MBMV (1), 2001)

Implementation of Read- k-times BDDs on Top of Standard BDD Packages. - Wolfgang Günther 001; Rolf Drechsler (VLSI Design, 2001)

Performance Driven Optimization for MUX based FPGAs. - Wolfgang Günther 001; Rolf Drechsler (VLSI Design, 2001)

History-based dynamic BDD minimization. - Rolf Drechsler; Wolfgang Günther 001 (Integr., 2001)

Using lower bounds during dynamic BDD minimization. - Rolf Drechsler; Wolfgang Günther 001; Fabio Somenzi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf. - Wolfgang Günther 001 (2001)

Crossing Reduction by Windows Optimization. - Thomas Eschbach; Wolfgang Günther 001; Rolf Drechsler; Bernd Becker 001 (GD, 2002)

Minimization of Word-Level Decision Diagrams. - Rolf Drechsler; Wolfgang Günther 001; Stefan Höreth (Integr., 2002)

Minimization of free BDDs. - Wolfgang Günther 001; Rolf Drechsler (Integr., 2002)

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. - Mitchell A. Thornton; Rolf Drechsler; Wolfgang Günther 001 (VLSI Design, 2002)

Combination of Lower Bounds in Exact BDD Minimization. - Rüdiger Ebendt; Wolfgang Günther 001; Rolf Drechsler (DATE, 2003)

The Case for 2-POF. - Ilia Polian; Wolfgang Günther 001; Bernd Becker 001 (MBMV, 2003)

Cross Reduction for Orthogonal Circuit Visualization. - Thomas Eschbach; Wolfgang Günther 001; Bernd Becker 001 (VLSI, 2003)

Pattern-based verification of connections to intellectual property cores. - Ilia Polian; Wolfgang Günther 001; Bernd Becker 001 (Integr., 2003)

Recursive bi-partitioning of netlists for large number of partitions. - Rolf Drechsler; Wolfgang Günther 001; Thomas Eschbach; Lothar Linhard; Gerhard Angst (J. Syst. Archit., 2003)

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. - Wolfgang Günther 001; Rolf Drechsler (IEEE Trans. Computers, 2003)

An improved branch and bound algorithm for exact BDD minimization. - Rüdiger Ebendt; Wolfgang Günther 001; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimization of the expected path length in BDDs based on local changes. - Rüdiger Ebendt; Wolfgang Günther 001; Rolf Drechsler (ASP-DAC, 2004)

Orthogonal hypergraph routing for improved visibility. - Thomas Eschbach; Wolfgang Günther 001; Bernd Becker 001 (ACM Great Lakes Symposium on VLSI, 2004)

Efficient (Non-)Reachability Analysis of Counterexamples. - Rolf Drechsler; Wolfgang Günther 001; Burkhard Stubert (MBMV, 2004)

Some Common Synthesis-Simulation-Mismatches. - Wolfgang Günther 001; Stefan Höreth (MBMV, 2004)

Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. - Thomas Eschbach; Wolfgang Günther 001; Bernd Becker 001 (VLSI Design, 2005)

Combining ordered best-first search with branch and bound for exact BDD minimization. - Rüdiger Ebendt; Wolfgang Günther 001; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Orthogonal Hypergraph Drawing for Improved Visibility. - Thomas Eschbach; Wolfgang Günther 001; Bernd Becker 001 (J. Graph Algorithms Appl., 2006)