Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness. - Torsten Mahnke; Sebastian Panenka; Martin Embacher; Walter Stechele; Wolfgang Hoeld (ICECS, 2002)

Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis. - Torsten Mahnke; Walter Stechele; Martin Embacher; Wolfgang Hoeld (ICECS, 2002)

Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. - Torsten Mahnke; Walter Stechele; Wolfgang Hoeld (PATMOS, 2002)