A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

An analysis of an inexpensive memory test solution. - Ryan Pennucci; Ryan Jurasek; Wolfgang Hokenmaier; Lester Patrick; Jacob Bucci; Donald Labrecque; David Kinney (NATW, 2018)

Verification and Testing Considerations of an In-Memory AI Chip. - Marcia Golmohamadi; Ryan Jurasek; Wolfgang Hokenmaier; Donald Labrecque; Ruoyu Zhi; Bret Dale; Nibir Islam; Dave Kinney; Angela Johnson (NATW, 2020)

Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator. - Wolfgang Hokenmaier; Ryan Jurasek; Elijah F. W. Bowen; R. Granger; D. Odom (CoRR, 2024)