CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. - Uwe Hübner; Wolfgang Meyer 002; Heinrich Theodor Vierhaus (Microprocess. Microprogramming, 1992)

Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. - Wolfgang Meyer 002; Raul Camposano (DAC, 1993)

CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. - Heinrich Theodor Vierhaus; Wolfgang Meyer 002; Uwe Gläser (ITC, 1993)

Fault behavior and testability of asynchronous CMOS circuits. - Heinrich Theodor Vierhaus; Wolfgang Meyer 002; Uwe Gläser; Raul Camposano (Microprocess. Microprogramming, 1993)

Hierarchische Mehr-Ebenen-Fehlersimulation mit Modellen der Schalter-Ebene. - Wolfgang Meyer 002 (Oldenbourg, 1994)

Active timing multilevel fault-simulation with switch-level accuracy. - Wolfgang Meyer 002; Raul Camposano (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A system for compiling and debugging structured data processing controllers. - Andrew Seawright; Joseph Buck; Ulrich Holtmann; Wolfgang Meyer 002; Barry M. Pangrle; Rob Verbrugghe (EURO-DAC, 1996)

Design and Synthesis of Array Structured Telecommunication Processing Applications. - Wolfgang Meyer 002; Andrew Seawright; Fumiya Tada (DAC, 1997)

Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions. - Andrew Seawright; Wolfgang Meyer 002 (DAC, 1998)