A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. - Philipp Salz; A. Frisch; Wolfgang Penth; J. Noack; T. Kalla; Rolf Sautter; Michael Kugel; Otto A. Torreiter; G. Sapp; Mike Lee; Eric Fluhr; A. Rozenfeld; et al. (ESSCIRC, 2017)