SESPATH: An ER Manipulation Language. - Wolfgang Roesner (ER, 1985)

The logic design language and verification environment for the VLSI-/370. - Wolfgang Roesner (Microprocess. Microprogramming, 1988)

EDA in IBM: past, present, and future. - John A. Darringer; Evan E. Davidson; David J. Hathaway; Bernd Koenemann; Mark A. Lavin; Joseph K. Morrell; Khalid Rahmat; Wolfgang Roesner; Erich C. Schanzenbach; Gustavo E. Téllez; Louise Trevillyan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. - John M. Ludden; Wolfgang Roesner; Gerry M. Heiling; John R. Reysa; Jonathan R. Jackson; Bing-Lun Chu; Michael L. Behm; Jason Baumgartner; Richard D. Peterson; Jamee Abdulhafiz; William E. Bucy; John H. Klaus; et al. (IBM J. Res. Dev., 2002)

What Is beyond the RTL Horizon for Microprocessor and System Design? - Wolfgang Roesner (CHARME, 2003)

Configurable system simulation model build comprising packaging design data. - Hans-Werner Anderson; Hans Kriese; Wolfgang Roesner; Klaus-Dieter Schubert (IBM J. Res. Dev., 2004)

ESL hand-off: fact or EDA fiction? - Hiroyuki Yagi; Wolfgang Roesner; Tim Kogel; Eshel Haritan; Hidekazu Tangi; Michael McNamara; Gary Smith 001; Nikil D. Dutt; Giovanni Mancini (DAC, 2008)

Functional verification of the IBM System z10 processor chipset. - Christopher A. Krygowski; Dean G. Bair; Rebecca M. Gott; Mark H. Decker; A. V. Giri; Christian Habermann; Matthias Heizmann; Stefan Letz; William J. Lewis; Steven M. Licker; H. Mallar; Edward C. McCain; et al. (IBM J. Res. Dev., 2009)

Post-Silicon Validation of the IBM POWER8 Processor. - Amir Nahir; Manoj Dusanapudi; Shakti Kapoor; Kevin Reick; Wolfgang Roesner; Klaus-Dieter Schubert; Keith Sharp; Greg Wetli (DAC, 2014)

Designer-level verification: an industrial experience story. - Stephen Bergman; Gabor Bobok; Walter Kowalski; Shlomit Koyfman; Shiri Moran; Ziv Nevo; Avigail Orni; Viresh Paruthi; Wolfgang Roesner; Gil Shurek; Vasantha Vuyyuru (DATE, 2015)

Verification at RTL Using Separation of Design Concerns. - Maya H. Safieddine; Fadi A. Zaraket; Rouwaida Kanj; Ali S. Elzein; Wolfgang Roesner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs. - Arun Joseph; Pretty Mariam Jacob; Matthias Klein; Wolfgang Roesner (IEEE Des. Test, 2024)