VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors. - Wolfram Drescher; Kay Bachmann; Gerhard P. Fettweis (ICASSP, 1997)

An architectural study of a digital signal processor for block codes. - Wolfram Drescher; Menno Mennenga; Gerhard P. Fettweis (ICASSP, 1998)

A platform-based highly parallel digital signal processor. - Thomas Richter; Wolfram Drescher; Frank Engel; S. Kobayashi; Vladimir Nikolajevic; Matthias Weiss; Gerhard P. Fettweis (CICC, 2001)

Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis. - Marko Rößler; Hailu Wang; Ulrich Heinkel; Nur Engin; Wolfram Drescher (FDL, 2009)