A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. - Dongsuk Shin; Won-Joo Yun; Hyun-Woo Lee; Young-Jung Choi; Suki Kim; Chulwoo Kim (ESSCIRC, 2008)

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. - Dong-Uk Lee; Shin-Deok Kang; Nak-Kyu Park; Hyun-Woo Lee; Young-Kyoung Choi; Jung-Woo Lee; Seung-Wook Kwack; Hyeong-Ouk Lee; Won-Joo Yun; Sang-Hoon Shin; Kwan-Weon Kim; Young-Jung Choi; et al. (ISSCC, 2008)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder. - Won-Joo Yun; Dongsuk Shin; Suki Kim (IEICE Electron. Express, 2008)

A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. - Dongsuk Shin; Jabeom Koo; Won-Joo Yun; Young-Jung Choi; Chulwoo Kim (ISCAS, 2009)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)

Coverage expandable current type code controlled DCC with TDC-based range selector. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Young-Jung Choi; Suki Kim (IEICE Electron. Express, 2009)

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. - Hyun-Woo Lee; Yong-Hoon Kim; Won-Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan-Weon Kim; Jun Hyun Chun; et al. (ISCAS, 2010)

A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. - Won-Joo Yun; Hiroki Ishikuro; Tadahiro Kuroda (A-SSCC, 2011)

A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Suki Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. - Won-Joo Yun; Shinya Nakano; Wataru Mizuhara; Atsutake Kosuge; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. - Yuki Urano; Won-Joo Yun; Tadahiro Kuroda; Hiroki Ishikuro (ISCAS, 2013)

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs. - Won-Joo Yun; Indal Song; Hanki Jeoung; Hundai Choi; Seok-Ho Lee; Jun-Bae Kim; Chi-Wook Kim; Jung-Hwan Choi; Seong-Jin Jang; Joo-Sun Choi (ISSCC, 2015)

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM). - Hyunui Lee; Sukyong Kang; Hye-Seung Yu; Won-Joo Yun; Jae-Hun Jung; Sungoh Ahn; Wang-Soo Kim; Beomyong Kil; Yoo-Chang Sung; Sang-Hoon Shin; Yong-Sik Park; Yong-Hwan Kim; et al. (A-SSCC, 2016)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (ISSCC, 2016)

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (IEEE J. Solid State Circuits, 2017)