A QNAR-AGC estimator with reduced arithmetic complexity. - Won Lee; Kyu Park; Song Park (IEEE Trans. Acoust. Speech Signal Process., 1985)

Process variation tolerant all-digital multiphase DLL for DDR3 interface. - Heechai Kang; Kyungho Ryu; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (CICC, 2010)

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. - Heechai Kang; Kyungho Ryu; Dong-Hoon Jung; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Won Lee; Seong-Ook Jung (CICC, 2013)

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. - Kwanyeob Chae; JongRyun Choi; Shinyoung Yi 002; Won Lee; Sanghoon Joo; Hyunhyuck Kim; Hyungkwon Yi; Yoonjee Nam; Jinho Choi; Sanghune Park; Sanghyun Lee (ESSCIRC, 2016)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

Networks never rest: An investigation of network evolution in three species of animals. - Ivan Chase; Darius Coelho; Won Lee; Klaus Mueller 001; James P. Curley (Soc. Networks, 2022)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)