Integrated interconnect circuit modeling for VLSI design. - Won-Young Jung; Ghun-Up Cha; Young-Bae Kim; Jun-Ho Baek; Choon-Kyung Kim (ASP-DAC, 1995)

Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards. - Yong-Ju Kim; Won-Young Jung; Jae-Kyung Wee (IEICE Trans. Electron., 2006)

A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. - Ji-Hoon Lim; Jong-Chan Ha; Won-Young Jung; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Electron., 2007)

Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches. - Won-Young Jung; Hyungon Kim; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits. - Jae-Young Park; Jong-Kyu Song; Chang-Soo Jang; San-Hong Kim; Won-Young Jung; Taek-Soo Kim (IEICE Trans. Electron., 2009)

On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs. - Jae-Young Park; Jong-Kyu Song; Dae-Woo Kim; Chang-Soo Jang; Won-Young Jung; Taek-Soo Kim (IEICE Trans. Electron., 2010)

A Precision Floating-Gate Mismatch Measurement Technique for Analog Application. - Won-Young Jung; Jong-Min Kim; Jin-Soo Kim; Taek-Soo Kim (IEICE Trans. Electron., 2011)

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process. - Jae-Young Park; Dae-Woo Kim; Young-Sang Son; Jong-Kyu Song; Chang-Soo Jang; Won-Young Jung (IEICE Trans. Electron., 2011)

A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. - Ji-Hoon Lim; Won-Young Jung; Yong-Ju Kim; Inchae Song; Jae-Kyung Wee (IEICE Trans. Electron., 2013)