13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)