An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. - Wonseok Choi 004; Jongsun Park 001 (ISOCC, 2017)

Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators. - Wonseok Choi 004; Dongyeob Shin; Jongsun Park 001; Swaroop Ghosh (DAC, 2019)

Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators. - Dongyeob Shin; Wonseok Choi 004; Jongsun Park 001; Swaroop Ghosh (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Exploiting Retraining-Based Mixed-Precision Quantization for Low-Cost DNN Accelerator Design. - Nahsung Kim; Dongyeob Shin; Wonseok Choi 004; Geonho Kim; Jongsun Park 001 (IEEE Trans. Neural Networks Learn. Syst., 2021)