A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. - Jaewook Kim; Wonsik Yu; Hyun-Kyu Yu; SeongHwan Cho (ISSCC, 2011)

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (VLSIC, 2012)

A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (CICC, 2013)

A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (IEEE J. Solid State Circuits, 2013)

A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. - Wonsik Yu; Jaewook Kim; KwangSeok Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. - KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE J. Solid State Circuits, 2014)

A 148fsrms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2015)

A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. - Jungho Kim; Young-Hwa Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. - Dongin Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. - Dokyung Lim; Sounghun Shin; Seungmin Lee; Kihyun Kwon; Jeongmin An; Wonsik Yu; Chanyoung Jeong; WooSeok Kim; Michael Choi; Jongshin Shin (ISSCC, 2022)

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. - Jusung Lee; Youngwoo Jo; Wonsik Yu; WooSeok Kim; Michael Choi; Sanghune Park; Jongshin Shin (CICC, 2023)

A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology. - Subhadeep Datta; Arnab Banerjee; Ayush Tripathi; Dongmin Kang; Leesunghyuck; Hasung Lim; Wonsik Yu; Kgj Vishnu; Chanyoung Jeong; Sumanth Chakkirala; Avneesh Singh Verma; Sachin Kashyap; et al. (A-SSCC, 2024)