T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training. - Jaehoon Heo; Junsoo Kim 002; Wontak Han; Sukbin Lim; Joo-Young Kim 001 (CICC, 2022)

Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training. - Wontak Han; Jaehoon Heo; Junsoo Kim 002; Sukbin Lim; Joo-Young Kim 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning. - Jung-Hoon Kim; Jaehoon Heo; Wontak Han; Jaeuk Kim; Joo-Young Kim 001 (VLSI Technology and Circuits, 2023)

Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics. - Donghyuk Kim; Jae-Young Kim; Wontak Han; Jongsoon Won; Haerang Choi; Yongkee Kwon; Joo-Young Kim 001 (CoRR, 2023)

T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training. - Jaehoon Heo; Junsoo Kim 002; Sukbin Lim; Wontak Han; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2023)

SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning. - Jaehoon Heo; Jung-Hoon Kim; Wontak Han; Jaeuk Kim; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2024)

SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation. - Wontak Han; Hyunjun Cho; Donghyuk Kim; Joo-Young Kim 001 (IEEE Trans. Computers, 2025)