Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. - Woo-Rham Bae; Byoung-Joo Yoo; Deog-Kyoon Jeong (ISOCC, 2012)

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (A-SSCC, 2014)

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. - Woo-Rham Bae; Deog-Kyoon Jeong; Byoung-Joo Yoo (DDECS, 2014)

A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth. - Woo-Rham Bae; Deog-Kyoon Jeong (ICEIC, 2014)

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2014)

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS. - Yoonsoo Kim; Woo-Rham Bae; Deog-Kyoon Jeong (ISCAS, 2014)

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. - Byoung-Joo Yoo; Woo-Rham Bae; Jiho Han; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (A-SSCC, 2015)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

A low-power pulse position modulation transceiver. - Woo-Rham Bae; Chang-Soo Yoon; Deog-Kyoon Jeong (ISCAS, 2015)

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Haram Ju; Jinhyung Lee; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (ISCAS, 2015)

A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances. - Woo-Rham Bae; Deog-Kyoon Jeong (Int. J. Circuit Theory Appl., 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (A-SSCC, 2016)

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. - Haram Ju; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Yoonsoo Kim; Hankyu Chi; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. - Kwanseo Park; Woo-Rham Bae; Deog-Kyoon Jeong (CICC, 2017)

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. - Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (Sensors, 2017)

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. - Woo-Rham Bae; Borivoje Nikolic; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. - Stevo Bailey; Jaeduk Han; Paul Rigge; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (A-SSCC, 2018)

BAG2: A process-portable framework for generator-based AMS circuit design. - Eric Chang; Jaeduk Han; Woo-Rham Bae; Zhongkai Wang; Nathan Narevsky; Borivoje Nikolic; Elad Alon (CICC, 2018)

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. - Angie Wang; Woo-Rham Bae; Jaeduk Han; Stevo Bailey; Paul Rigge; Orhan Ocal; Zhongkai Wang; Kannan Ramchandran; Elad Alon; Borivoje Nikolic (ESSCIRC, 2018)

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Jinhyung Lee; Jeongho Hwang; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2018)

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique. - Woo-Rham Bae; Kyung Jean Yoon; Taeksang Song; Borivoje Nikolic (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Han-Gon Ko; Jinhyung Lee; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Woo-Rham Bae; Jun-Eun Park; Chang-Soo Yoon; Jungmin Yoon; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Jaeduk Han; Deog-Kyoon Jeong (IEEE Trans. Ind. Electron., 2018)

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. - Jaeduk Han; Eric Chang; Stevo Bailey; Zhongkai Wang; Woo-Rham Bae; Angie Wang; Nathan Narevsky; Amy Whitcombe; Pengpeng Lu; Borivoje Nikolic; Elad Alon (CICC, 2019)

Reference Spur Reduction Techniques for a Phase-Locked Loop. - Han-Gon Ko; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Access, 2019)

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. - Steven Bailey; Paul Rigge; Jaeduk Han; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (IEEE J. Solid State Circuits, 2019)

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. - Angie Wang; Woo-Rham Bae; Jaeduk Han; Stevo Bailey; Orhan Ocal; Paul Rigge; Zhongkai Wang; Kannan Ramchandran; Elad Alon; Borivoje Nikolic (IEEE J. Solid State Circuits, 2019)

Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal-Oxide-Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network-Based Stochastic Learning. - Woorham Bae; Kyung Jean Yoon (Adv. Intell. Syst., 2020)

State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey. - Woorham Bae (ISCAS, 2021)

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woo-Rham Bae; Sean Huang; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; Borivoje Nikolic (ISSCC, 2021)

An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser. - Mark T. Wade; Erik Anderson; Shahab Ardalan; Woorham Bae; Behrooz Beheshtian; Sidney Buchbinder; Ken Chang; Paulo Chao; Haritha Eachempatti; John Frey; Eric Jan; Austin Katzin; et al. (OFC, 2021)

Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing. - Mark Wade; Daniel Jeong; Byungchae Kim; Mason Zhang; Woorham Bae; Chong Zhang; Pavan Bhargava; Derek Van Orden; Shahab Ardalan; Chandarasekaran Ramamurthy; Erik Anderson; Austin Katzin; et al. (VLSI Circuits, 2021)

Today's computing challenges: opportunities for computer hardware design. - Woo-Rham Bae (PeerJ Comput. Sci., 2021)

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. - Jaeduk Han; Woo-Rham Bae; Eric Chang; Zhongkai Wang; Borivoje Nikolic; Elad Alon (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures. - Woorham Bae (IEEE Access, 2022)

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woorham Bae; Sean Huang; Vladimir M. Milovanovic; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; et al. (IEEE J. Solid State Circuits, 2022)

A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets. - Pavan Bhargava; Daniel Jeong; Eric Jan; Derek Van Orden; Derek Kita; Hayk Gevorgyan; Sidney Buchbinder; Anatoly Khilo; Woorham Bae; Sung-Jin Kim; John Michael Fini; Norman Chan; et al. (VLSI Technology and Circuits, 2024)

A UCIe Optical I/O Retimer Chiplet for AI Scale-up Fabrics. - Pavan Bhargava; Sidney Buchbinder; Dorde Gluhovic; Kaisarbek Omirzakhov; Ayan Biswas; Daniel Jeong; Clay Pearson; Austin Katzin; Eric Jan; Derek Van Orden; Hayk Gevorgyan; Anatoly Khilo; et al. (OFC, 2025)