Automated generation of product use case scenarios in product line development. - Woo-Seok Choi; Sungwon Kang; Ho-Jin Choi; Jongmoon Baik (CIT, 2008)

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. - Sang-Yoon Lee; Hyung-Rok Lee; Young-Ho Kwak; Woo-Seok Choi; Byoung-Joo Yoo; Daeyun Shim; Chulwoo Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Tejasvi Anand; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2014)

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. - Guanghua Shu; Saurabh Saxena; Woo-Seok Choi; Mrunmay Talegaonkar; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. - Woo-Seok Choi; Guanghua Shu; Mrunmay Talegaonkar; Yubo Liu; Da Wei; Luca Benini; Pavan Kumar Hanumolu (ISSCC, 2015)

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Seong Joong Kim; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2015)

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. - Woo-Seok Choi; Tejasvi Anand; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Romesh Kumar Nandwana; Ahmed Elkholy; Da Wei; Timir Nandi; Pavan Kumar Hanumolu (ISSCC, 2016)

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. - Seong Joong Kim; Woo-Seok Choi; Robert C. N. Pilawa-Podgurski; Pavan Kumar Hanumolu (CICC, 2017)

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. - Junheng Zhu; Makrand Mahalley; Guanghua Shu; Woo-Seok Choi; Romesh Kumar Nandwana; Ahmed Elkholy; Bibhudatta Sahoo 002; Pavan Kumar Hanumolu (CICC, 2017)

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. - Romesh Kumar Nandwana; Saurabh Saxena; Ahmed Elkholy; Mrunmay Talegaonkar; Junheng Zhu; Woo-Seok Choi; Ahmed Elmallah; Pavan Kumar Hanumolu (ISSCC, 2017)

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

Design of energy-efficient high-speed wireline transceiver - Woo-Seok Choi (2017)

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. - Ahmed Elmallah; Mostafa Gamal Ahmed; Ahmed Elkholy; Woo-Seok Choi; Pavan Kumar Hanumolu (CICC, 2018)

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (CICC, 2018)

Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. - Woo-Seok Choi; Matthew Tomei; Jose Rodrigo Sanchez Vicarte; Pavan Kumar Hanumolu; Rakesh Kumar 002 (ISCA, 2018)

A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. - Woo-Seok Choi; Guanghua Shu; Mrunmay Talegaonkar; Yubo Liu; Da Wei; Luca Benini; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. - Seong Joong Kim; Woo-Seok Choi; Robert C. N. Pilawa-Podgurski; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 15-Gb/s Sub-Baud-Rate Digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

A 0.016 mm2 0.26- $ mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. - Junheng Zhu; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. - Dongwook Kim; Mostafa Gamal Ahmed; Woo-Seok Choi; Ahmed Elkholy; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2020)

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. - Woonghee Lee 005; Minkyo Shim; Yunhee Lee; Heejin Yang; Han-Gon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (ESSCIRC, 2021)

Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. - Joonghyun Song; Jiwon Shin; Hanseok Kim; Woo-Seok Choi (AICAS, 2022)

Improving Spiking Neural Network Accuracy Using Time-based Neurons. - Hanseok Kim; Woo-Seok Choi (ISCAS, 2022)

Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter. - Honggyoo Ahn; Joonghyun Song; Woo-Seok Choi (ISOCC, 2022)

Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit. - Hyunjun Park; Woo-Seok Choi (ISOCC, 2022)

Impact of Oscillator Phase Noise on Time-Domain SNN Performance. - Jia Park; Woo-Seok Choi (ISOCC, 2022)

A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion. - Joonghyun Song; Woo-Seok Choi (ISOCC, 2022)

0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. - Yunhee Lee; Woonghee Lee 005; Minkyo Shim; Soyeong Shin; Woo-Seok Choi; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. - Young-Ha Hwang; Jonghyun Oh; Woo-Seok Choi; Deog-Kyoon Jeong; Jun-Eun Park (IEEE J. Solid State Circuits, 2022)

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. - Hyojun Kim; Woosong Jung; Kwandong Kim; Sungwoo Kim 001; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. - Woonghee Lee 005; Minkyo Shim; Yunhee Lee; Heejin Yang; Soyeong Shin; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. - Daeho Yun; Eonhui Lee; Woosong Jung; Kahyun Kim; Kyung-Min Beak; Jihee Kim; Hyun Bae Lee; Byeongseon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. - Daeho Yun; Minsu Park; Kahyun Kim; Kyungmin Baek; Eonhui Lee; Woo-Seok Choi; Deog-Kyoon Jeong (A-SSCC, 2023)

Fast Performance Evaluation Methodology for High-speed Memory Interfaces. - Taehoon Kim; Yoona Lee; Woo-Seok Choi (DATE, 2023)

A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM. - Jiwon Shin; Joonghyun Song; Jihee Kim; Woo-Seok Choi (ESSCIRC, 2023)

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. - Kahyun Kim; Daeho Yun; Kyungmin Baek; Woo-Seok Choi; Deog-Kyoon Jeong (ISCAS, 2023)

A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method. - Jihee Kim; Woo-Seok Choi (ISOCC, 2023)

Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function. - Taehoon Kim; Woo-Seok Choi (ISOCC, 2023)

An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism. - Jia Park; Woo-Seok Choi (ISOCC, 2023)

Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis. - Hyeri Roh; Woo-Seok Choi (ISOCC, 2023)

A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors. - Jeongeun Song; Sunyoung Lee; Minseok Shin; Ohjun Kwon; Hansang Kim; Yujin Park; Gyubeom Hwang; Hyekyoung Jung; Hoesam Jeong; Changrock Song; Woo-Seok Choi (ISOCC, 2023)

JBNU at TREC 2023 Product Search Track. - Gi-taek An; Woo-Seok Choi; Jun-Yong Park; Kyung-Soon Lee (TREC, 2023)

Sagnac Effect Compensations and Locked States in a Ring Laser Gyroscope. - Woo-Seok Choi; Kyu-Min Shim; Kyung-Ho Chong; Jun-Eon An; Cheon-Joong Kim; Byung-Yoon Park (Sensors, 2023)

Phase Noise Analysis for Stochastically Injected Oscillators. - Jiwon Shin; Woo-Seok Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Verification and performance comparison of CNN-based algorithms for two-step helmet-wearing detection. - Ju-Yeon Lee; Woo-Seok Choi; Sang-Hyun Choi (Expert Syst. Appl., 2023)

A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection. - Hyeri Roh; Woo-Seok Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. - Kwang-Hoon Lee; Jung-Hun Park; Yongjae Lee; Yeonggeun Song; Seungha Roh; Minkyo Shim; Yoonho Song; Woosong Jung; Young-Ha Hwang; Jonghyun Oh; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. - Hyeri Roh; Woo-Seok Choi (ICCAD, 2024)

Device Parameter Extraction Method for Training Performance Predicting Models. - Minjeong Kim; Taehoon Kim; Woo-Seok Choi (ISOCC, 2024)

Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis. - Hyeri Roh; Woo-Seok Choi (ISOCC, 2024)

DVSMOT: Dual View Sharing for Enhanced Multi-Object Tracking and ID Switch Reduction. - Heon Jun Shin; Joohyung Oh; Woo-Seok Choi; Joong Hun Cho; Yeonseok Lee; Tae-Kyung Kim (BigComp, 2025)

A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. - Hyun-Seok Choi; Sunki Cho; Sanghee Lee 002; Hyeri Roh; Jeongeun Song; Honggyoo Ahn; Jihee Kim; Minchang Kim; Hankyu Chi; Deog-Kyoon Jeong; Woo-Seok Choi (CICC, 2025)

ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies. - Taehoon Kim; Minjeong Kim; Hankyu Chi; Byungjun Kang; Eunji Song; Woo-Seok Choi (DATE, 2025)

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. - Boram Kim; Hankyu Chi; Hyeongjun Ko; Sang-Yeon Byeon; Sungkwon Lee; Changhyun Pyo; Seulgi Kim; Byungjun Kang; Eunji Song; Kwangjin Na; Jin-Youp Cha; Hyesoo Kim; et al. (ISSCC, 2025)

22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces. - Kahyun Kim; Jung-Hun Park; Ha-Jung Park; Jia Park; Jihee Kim; Woo-Seok Choi (ISSCC, 2025)

Implementing FFE-MLSD With Improved BER and Reduced Complexity for Long-Reach PAM4 Wireline Receivers. - Hanseok Kim; Sihyun Lee; Piljun Jeong; Jaeha Kim; Woo-Seok Choi (IEEE Access, 2025)

A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution. - Jihee Kim; Jia Park; Jiwon Shin; Hanseok Kim; Kahyun Kim; Haengbeom Shin; Ha-Jung Park; Woo-Seok Choi (IEEE J. Solid State Circuits, 2025)

A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces. - Jihee Kim; Yunhee Lee; Hyun-Seok Choi; Yoona Lee; Sanghee Lee 002; Woo-Seok Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2025)