A control network architecture based on EIA-709.1 protocol for power line data communications. - Woo-Seop Kim; Lok-Won Kim; Chang-Eun Lee; Kyeong-Deok Moon; Suki Kim (IEEE Trans. Consumer Electron., 2002)

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling. - Jin-Hyun Kim; Sua Kim; Woo-Seop Kim; Jung-Hwan Choi; Hong-Sun Hwang; Changhyun Kim; Suki Kim (IEEE J. Solid State Circuits, 2005)

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. - Kyu-Hyoun Kim; Young-Soo Sohn; Chan-Kyoung Kim; Moon-Sook Park; Dong-Jin Lee; Woo-Seop Kim; Changhyun Kim (IEEE J. Solid State Circuits, 2006)

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. - Kyu-Hyoun Kim; Hoeju Chung; Woo-Seop Kim; Moon-Sook Park; Young-Chan Jang; Jinyoung Kim; Hwan-Wook Park; Uksong Kang; Paul W. Coteus; Joo-Sun Choi; Changhyun Kim (IEEE J. Solid State Circuits, 2007)

8Gb 3D DDR3 DRAM using through-silicon-via technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Soon-Hong Ahn; Hoon Lee; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jin Ho Kim; Jae-Wook Lee 007; Han-Sung Joo; Woo-Seop Kim; et al. (ISSCC, 2009)

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. - Young-Chan Jang; Hoeju Chung; Youngdon Choi; Hwan-Wook Park; Jaekwan Kim 003; Soouk Lim; Jung Sunwoo; Moon-Sook Park; Hyung-Seuk Kim; Sang-Yun Kim; Yun-Sang Lee; Woo-Seop Kim; et al. (IEEE J. Solid State Circuits, 2009)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module. - Seung Mo Jung; Jong Hyun Seok; Ho Jin Yoo; Do Hyung Kim 002; You Keun Han; Woo-Seop Kim; Joo-Sun Choi; Jun Dong Cho (SoCC, 2013)

Review of Memory RAS for Data Centers. - Jiseong Lee; Min Joon Kim; Woo-Seop Kim; Yong Sin Kim (IEEE Access, 2023)