Verification methodology of compatible microprocessors. - Joon-Seo Yim; Chang-Jae Park; Woo-Seung Yang; Hun-Seung Oh; Hee-Choul Lee; Hoon Choi; Tae-Hoon Kim; Seungjong Lee; Nara Won; Yung-Hei Lee; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

A C-Based RTL Design Verification Methodology for Complex Microprocessor. - Joon-Seo Yim; Yoon-Ho Hwang; Chang-Jae Park; Hoon Choi; Woo-Seung Yang; Hun-Seung Oh; In-Cheol Park; Chong-Min Kyung (DAC, 1997)

Multi-thread VLIW processor architecture for HDTV decoding. - Hansoo Kim; Woo-Seung Yang; Myoung-Cheol Shin; Seung-Jai Min; Seong-Ok Bae; In-Cheol Park (CICC, 2000)

Low-power high-level synthesis using latches. - Woo-Seung Yang; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 2001)

Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. - Young-Su Kwon; Woo-Seung Yang; Chong-Min Kyung (VLSI-SOC, 2003)

Communication-efficient hardware acceleration for fast functional simulation. - Young-Il Kim; Woo-Seung Yang; Young-Su Kwon; Chong-Min Kyung (DAC, 2004)

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. - Jae-Gon Lee; Woo-Seung Yang; Young-Su Kwon; Young-Il Kim; Chong-Min Kyung (ASP-DAC, 2005)

Conscep: a Configurable Soc Emulation Platform for C-based Fast Prototyping. - Woo-Seung Yang; Chong-Min Kyung (J. Circuits Syst. Comput., 2005)