Design of low-jitter 1-GHz phase-locked loops for digital clock generation. - Woogeun Rhee (ISCAS (2), 1999)

An on-chip phase compensation technique in fractional-N frequency synthesis. - Woogeun Rhee; Akbar Ali (ISCAS (3), 1999)

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator. - Woogeun Rhee; Bang-Sup Song; Akbar Ali (IEEE J. Solid State Circuits, 2000)

Multi-Bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers - Woogeun Rhee (2001)

A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer. - Rahul Magoon; Alyosha C. Molnar; Jeff Zachan; Geoff Hatcher; Woogeun Rhee (IEEE J. Solid State Circuits, 2002)

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution. - Woogeun Rhee; Biagio Bisanti; Akbar Ali (IEEE J. Solid State Circuits, 2002)

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. - Woogeun Rhee; Herschel A. Ainspan; Sergey V. Rylov; Alexander V. Rylyakov; Michael P. Beakes; Daniel J. Friedman; Sudhir M. Gowda; Mehmet Soyuer (CICC, 2003)

A semi-digital delay-locked loop using an analog-based finite state machine. - Woogeun Rhee; Benjamin D. Parker; Daniel J. Friedman (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. - Troy J. Beukema; Michael Sorna; Karl Selander; Steven Zier; Brian L. Ji; Phil Murfet; James Mason; Woogeun Rhee; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes (IEEE J. Solid State Circuits, 2005)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. - Baoyong Chi; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2007)

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. - Yong Liu 023; Woogeun Rhee; Daniel J. Friedman; Donhee Ham (ISSCC, 2007)

An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. - Babak Soltanian; Herschel A. Ainspan; Woogeun Rhee; Daniel J. Friedman; Peter R. Kinget (IEEE J. Solid State Circuits, 2007)

A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering. - Xueyi Yu; Yuanfeng Sun; Li Zhang 023; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2008)

Experimental Analysis of Substrate Noise Effect on PLL Performance. - Woogeun Rhee; Keith A. Jenkins; John C. Liobe; Herschel A. Ainspan (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Transient Analysis of Nonlinear Settling Behavior in Charge-pump Phase-locked Loop Design. - Rui He; Jun Li 024; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2009)

Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL. - Jian Qiao; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2009)

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation. - Xueyi Yu; Woogeun Rhee; Zhihua Wang 001; Jung-Bae Lee; Changhyun Kim (ISSCC, 2009)

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops. - Li Zhang 023; Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Dawn Wang; Zhihua Wang 001; Hongyi Chen (IEEE J. Solid State Circuits, 2009)

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Hyung Ki Ahn; Byeong-Ha Park; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis. - Jun Li 024; Ni Xu; Yuanfeng Sun; Woogeun Rhee; Zhihua Wang 001 (APCCAS, 2010)

Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit. - Yutao Liu; Ni Xu; Woogeun Rhee; Ziqiang Wang; Zhihua Wang 001 (APCCAS, 2010)

Low power, non invasive UWB systems for WBAN and biomedical applications. - Woogeun Rhee; Ni Xu; Bo Zhou 008; Zhihua Wang 001 (ICTC, 2010)

A relaxation oscillator with multi-phase triangular waveform generation. - Hang Lv 002; Bo Zhou 008; Woogeun Rhee; Yongming Li 004; Zhihua Wang 001 (ISCAS, 2011)

A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid. - Zhuo Zhang; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2011)

Semidigital PLL Design for Low-Cost Low-Power Clock Generation. - Ni Xu; Woogeun Rhee; Zhihua Wang 001 (J. Electr. Comput. Eng., 2011)

A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning. - Yuanfeng Sun; Jian Qiao; Xueyi Yu; Woogeun Rhee; Byeong-Ha Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A pulse-shaped power amplifier with dynamic bias switching for IR-UWB transmitters. - Shuli Geng; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2012)

A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. - Ke Huang 003; Chen Jia; Xuqiang Zheng; Ni Xu; Chun Zhang; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2012)

A ΔΣ IR-UWB radar with sub-mm ranging capability for human body monitoring systems. - Wei Zhang 078; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2012)

Session 26 overview: Short-range wireless transceivers: Wireless subcommittee. - Ranjit Gharpurey; Woogeun Rhee (ISSCC, 2012)

A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL. - Yizhi Han; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2012)

Clock/Frequency Generation Circuits and Systems. - Woogeun Rhee; Antonio Liscidini; Jae-Yoon Sim; Kenichi Okada 001; Sudhakar Pamarti (J. Electr. Comput. Eng., 2012)

Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). - Shen-Iuan Liu; Tsung-Hsien Lin; Woogeun Rhee (IEEE J. Solid State Circuits, 2012)

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. - Nan Qi; Yang Xu 005; Baoyong Chi; Yang Xu 039; Xiaobao Yu; Xing Zhang; Ni Xu; Patrick Chiang 001; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Gated FM-UWB System With Data-Driven Front-End Power Control. - Bo Zhou 008; Jian Qiao; Rui He; Jinghui Liu; Wei Zhang 078; Hang Lv 002; Woogeun Rhee; Yongming Li 004; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation. - Fei Chen 006; Yu Li; Deyuan Lin; Huiying Zhuo; Woogeun Rhee; Jongjin Kim 002; Dongwook Kim; Zhihua Wang 001 (CICC, 2013)

A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation. - Shuli Geng; Ni Xu; Jun Li 024; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2013)

An FM-UWB transceiver with M-PSK subcarrier modulation and regenerative FM demodulation. - Dang Liu; Fei Chen 006; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2013)

A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems. - Hang Lv 002; Bo Zhou 008; Dang Liu; Woogeun Rhee; Yongming Li 004; Zhihua Wang 001 (VLSI-DAT, 2013)

A Phase-Domain ΔΣ Ranging Method for FMCW Radar Receivers. - Wei Zhang 078; Xican Chen; Fei Chen 006; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Reconfigurable FM-UWB transmitter design for robust short range communications. - Bo Zhou 008; Woogeun Rhee; Dongwook Kim; Zhihua Wang 001 (Telecommun. Syst., 2013)

Introduction to the Special Section on the 2012 Asian Solid-State Circuits Conference (A-SSCC). - Chang-Hyun Kim; Hong June Park; Woogeun Rhee (IEEE J. Solid State Circuits, 2013)

A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications. - Yang Li; Ni Xu; Yining Zhang; Woogeun Rhee; Sanghoon Kang; Zhihua Wang 001 (A-SSCC, 2014)

Algorithm-Based Countermeasures against Power Analysis Attacks for Public-Key Cryptography SM2. - Xiaowei Han; Beibei Wang; An Wang 001; Liji Wu; Woogeun Rhee (CIS, 2014)

A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL. - Yanfeng Li; Ni Xu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2014)

A high efficiency robust IR-UWB receiver design for high data rate CM-range communications. - Dang Liu; Shuli Geng; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2014)

9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability. - Fei Chen 006; Yu Li; Dang Liu; Woogeun Rhee; Jongjin Kim 002; Dong-Wook Kim; Zhihua Wang 001 (ISSCC, 2014)

9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications. - Shuli Geng; Dang Liu; Yanfeng Li; Huiying Zhuo; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2014)

F5: Low-power radios for sensor networks. - Woogeun Rhee; Gangadhar Burra; Kazutami Arimoto; Pieter Harpe; Brian Otis; David Ruffieux (ISSCC, 2014)

A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC. - Wei Zhang 078; Yizhi Han; Fei Chen 006; Bo Zhou 008; Xican Chen; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2014)

A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS. - Huiying Zhuo; Yu Li; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2014)

A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation. - Ni Xu; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2014)

A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems. - Xican Chen; Wei Zhang 078; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems. - Yutao Liu; Yizhi Han; Woogeun Rhee; Tae-Young Oh; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. - Shuai Yuan 005; Ziqiang Wang; Xuqiang Zheng; Ke Huang 003; Ni Xu; Woogeun Rhee; Liji Wu; Chun Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications. - Chao Yang; Shaoquan Gao; Jingjing Dong; Hanjun Jiang; Woogeun Rhee; Zhihua Wang 001 (ASICON, 2015)

A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications. - Dang Liu; Xiaofeng Liu; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2015)

A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation. - Ni Xu; Yiyu Shen; Sitao Lv; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2015)

Phase-locked frequency synthesis and modulation for modern wireless transceivers. - Woogeun Rhee (CICC, 2015)

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path. - Xiaoyong Li; Woogeun Rhee; Wen Jia; Zhihua Wang 001 (ISCAS, 2015)

A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters. - Yiyu Shen; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2015)

A delta-sigma-based transmitter utilizing FIR-embedded digital power amplifiers. - Heng Liu; Hanjun Jiang; Yiyu Shen; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2015)

A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator. - Yanfeng Li; Yutao Liu; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2015)

A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications. - Shuli Geng; Dang Liu; Yanfeng Li; Huiying Zhuo; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2015)

A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. - Yudong Zhang 006; Woogeun Rhee; Taeik Kim; Hojin Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL. - Yining Zhang; Ranran Zhou; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2016)

EE4: Eureka! The best moments of solid-state circuit design in the 2000s. - Woogeun Rhee; Eric A. M. Klumperink; Hossein Hashemi 001 (ISSCC, 2016)

An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation. - Woogeun Rhee; Sitao Lv; Han Liu; Ni Xu; Zhihua Wang 001 (MWSCAS, 2016)

A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector. - Jianfu Lin; Zheng Song 002; Nan Qi; Woogeun Rhee; Baoyong Chi (A-SSCC, 2017)

Session 15 - Energy-efficient wireless for 5G and IoT. - Woogeun Rhee; Swaminathan Sankaran (CICC, 2017)

A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies. - Yining Zhang; Ranran Zhou; Woogeun Rhee; Zhihua Wang 001 (CICC, 2017)

A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. - Yudong Zhang 006; Xiaofeng Liu; Woogeun Rhee; Hanjun Jiang; Zhihua Wang 001 (ISCAS, 2017)

An energy/bandwidth/area efficient frequency-domain OOK transmitter with phase rotated modulation. - Ranran Zhou; Yining Zhang; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2017)

A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications. - Dang Liu; Xuwen Ni; Ranran Zhou; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2017)

A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL. - Yining Zhang; Ranran Zhou; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2017)

A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling. - Xican Chen; Yiyu Shen; Zhicheng Wang; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands. - Haixin Song; Dang Liu; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2018)

A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications. - Dang Liu; Xiaohua Huang; Zhendong Ding; Haixin Song; Woogeun Rhee; Zhihua Wang 001 (CICC, 2018)

A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems. - Xiaohua Huang; Han Liu; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2018)

A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector. - Jianfu Lin; Zheng Song 002; Nan Qi; Woogeun Rhee; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2018)

A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications. - Fei Chen 006; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 120 pJ/bit ΔΣ-Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier. - Yanshu Guo; Hanjun Jiang; Heng Liu; Zhaoyang Weng; Woogeun Rhee; Chun Zhang; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 1-GHz 1.6-mW Auto-Calibrated Bit Slicer for Energy/Envelope Detection Receivers. - Xiaohua Huang; Dang Liu; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna. - Zhaoyang Weng; Hanjun Jiang; Jingjing Dong; Yang Li; Jingyi Zheng; Yiyu Shen; Fule Li; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL. - Cong Ding 004; Haixin Song; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2019)

A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. - Xiaohua Huang; Kunnong Zeng; Yuguang Liu; Woogeun Rhee; Taeik Kim; Zhihua Wang 001 (CICC, 2019)

A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1+-Point Modulation. - Cong Ding 004; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2019)

A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering. - Xiaohua Huang; Kunnong Zeng; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2019)

A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity. - Yuguang Liu; Haixin Song; Kunnong Zeng; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2019)

Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation. - Yining Zhang; Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2019)

A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation. - Yining Zhang; Meng Ni; Xiaohua Huang; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2019)

A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range. - Yining Zhang; Haixin Song; Ranran Zhou; Woogeun Rhee; Inbo Shim; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity. - Haixin Song; Woogeun Rhee; Zhihua Wang 001 (CICC, 2020)

A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation. - Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2020)

A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation. - Xinyu Xu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2020)

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter. - Xiaohua Huang; Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2020)

A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection. - Haixin Song; Dang Liu; Yining Zhang; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2020)

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. - Xuqiang Zheng; Fangxu Lv; Lei Zhou 014; DanYu Wu; Jin Wu; Chun Zhang; Woogeun Rhee; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS. - Zixiang Wan; Xinyu Xu; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2021)

Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops. - Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2021)

A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation. - Xinyu Xu; Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 2.4-GHz Crystal-Less GFSK Receiver Using an Auxiliary Multiphase BBPLL for Digital Output Demodulation With Enhanced Frequency Scaling. - Jiahao Zhao; Yining Zhang; Kunnong Zeng; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection. - Bowen Wang 001; Cong Ding 004; Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (CICC, 2022)

A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection. - Bowen Wang 001; Haixin Song; Woogeun Rhee; Zhihua Wang 001 (CICC, 2022)

An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS. - Luhua Lin; Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2022)

A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction. - Jiahao Zhao; Xuansheng Ji; Su Han; Ziwei Wang; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2022)

An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin. - Su Han; Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2022)

Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). - Jung-Hwan Choi; Po-Chiun Huang; Shouyi Yin; Woogeun Rhee (IEEE J. Solid State Circuits, 2022)

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. - Meng Ni; Xiao Wang 021; Fule Li; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators. - Liqun Feng; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector. - Liqun Feng; Qianxian Liao; Woogeun Rhee; Zhihua Wang 001 (A-SSCC, 2023)

A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter. - Liqun Feng; Woogeun Rhee; Zhihua Wang 001 (CICC, 2023)

A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS. - Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (ESSCIRC, 2023)

A 405ps/20% Delay Range, 7.4mW/ns BPF-Based Delay Cell with ISI Mitigation for 7.5-8.5GHz IR-UWB Beamforming Receivers. - Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2023)

A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation. - Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2023)

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. - Sanghee Lee 002; Byungjun Kang; Woogeun Rhee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.6V Fully-Integrated BLE Transmitter in 65nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F2 PA Achieving 25% System Efficiency at 0dBm. - Liqun Feng; Qianxian Liao; Longhao Kuang; Jiahao Zhao; Woogeun Rhee; Zhihua Wang (A-SSCC, 2024)

A 3.4 mW ± 0.45 dB-Gain-Variation 6-10GHz Low-Noise Amplifier with Embedded Capacitive Feedback and RC Extension Network for Gb/s UWB Receivers. - Longhao Kuang; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2024)

14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS. - Liqun Feng; Xuansheng Ji; Longhao Kuang; Qianxian Liao; Su Han; Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2024)

A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter. - Liqun Feng; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2024)

A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection. - Bowen Wang 001; Cong Ding 004; Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation. - Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2024)

A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking. - Bo Zhou 004; Yifan Li; Zuhang Wang; Chen Wang 103; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2024)

An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS. - Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2024)

A Wide Tracking Range Heterodyne Phase-Tracking Receiver With 1-bit Phase-Domain Demodulation. - Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.5V 0.55mm2 Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT applications. - Liqun Feng; Xuansheng Ji; Qianxian Liao; Longhao Kuang; Yunzhao Nie; Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (CICC, 2025)

A 1.8Gb/s 8GHz PSK-UWB Transceiver with Extended PPM/PWM Modulation and Embedded Carrier Spreading. - Luhua Lin; Bowen Wang; Longhao Kuang; Woogeun Rhee; Zhihua Wang (CICC, 2025)

An Asynchronous RISC-V Processor Utilizing a Chisel-Based Desynchronization Flow. - Haoyang Huang; Jilin Zhang; Dexuan Huo; Qibang Sun; Woogeun Rhee; Hong Chen 002 (ISCAS, 2025)

Analysis and Design of Bias-Current-Free Hybrid Phase-Locked Loops with Multi-Phase Time-Interleaved Phase Detector. - Qibang Sun; Liqun Feng; Woogeun Rhee; Zhihua Wang (ISCAS, 2025)

An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation. - Liqun Feng; Xuansheng Ji; Longhao Kuang; Qianxian Liao; Su Han; Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2025)

A 7.5-GHz Frequency-Hopping CDMA UWB Transceiver for Secure Multi-Sensor Connectivity. - Luhua Lin; Bowen Wang 001; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Polar Phase-Tracking Receiver With Two-Point Injection Technique. - Xuansheng Ji; Jiahao Zhao; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2025)

A 27.9-mW 802.15.4/4z 1T2R Transceiver With FIR-Embedded Quadrature Hybrid Correlation and AoA Localization. - Yunzhao Nie; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2025)