High performance and low power FIR filter design based on sharing multiplication. - Jongsun Park 001; Woopyo Jeong; Hunsoo Choo; Hamid Mahmoodi-Meimand; Yongtao Wang; Kaushik Roy 001 (ISLPED, 2002)

Robust high-performance low-power carry select adder. - Woopyo Jeong; Kaushik Roy 001 (ASP-DAC, 2003)

Low Power Adder with Adaptive Supply Voltage. - Hiroaki Suzuki; Woopyo Jeong; Kaushik Roy 001 (ICCD, 2003)

Adaptive supply voltage technique for low swing interconnects. - Woopyo Jeong; Bipul Chandra Paul; Kaushik Roy 001 (ASP-DAC, 2004)

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (ICASSP (5), 2004)

Low-power carry-select adder using adaptive supply voltage based on input vector patterns. - Hiroaki Suzuki; Woopyo Jeong; Kaushik Roy 001 (ISLPED, 2004)

Computation sharing programmable FIR filter for low-power and high-performance applications. - Jongsun Park 001; Woopyo Jeong; Hamid Mahmoodi-Meimand; Yongtao Wang; Hunsoo Choo; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2004)

High-performance low-power dual transition preferentially sized (DTPS) logic. - Woopyo Jeong; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2005)

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. - Hiroaki Suzuki; Woopyo Jeong; Kaushik Roy 001 (IEICE Trans. Electron., 2007)

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (J. Signal Process. Syst., 2010)

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. - Chulbum Kim; Jinho Ryu; Tae-Sung Lee; Hyunggon Kim; Jaewoo Lim; Jaeyong Jeong; Seonghwan Seo; Hongsoo Jeon; Bokeun Kim; Inyoul Lee; Dooseop Lee; Pansuk Kwak; et al. (IEEE J. Solid State Circuits, 2012)

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. - Jae-Woo Im; Woopyo Jeong; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (ISSCC, 2015)

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (ISSCC, 2016)

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. - Woopyo Jeong; Jae-Woo Im; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (IEEE J. Solid State Circuits, 2016)

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. - Chulbum Kim; Ji-Ho Cho; Woopyo Jeong; Il-Han Park; Hyun Wook Park; Doo-Hyun Kim; Daewoon Kang; Sunghoon Lee; Ji-Sang Lee; Wontae Kim 004; Jiyoon Park; Yang-Lo Ahn; et al. (ISSCC, 2017)

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (IEEE J. Solid State Circuits, 2017)

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. - Chulbum Kim; Doo-Hyun Kim; Woopyo Jeong; Hyun-Jin Kim; Il-Han Park; Hyun Wook Park; Jong-Hoon Lee; Jiyoon Park; Yang-Lo Ahn; Ji Young Lee; Seungbum Kim; Hyun-Jun Yoon; et al. (IEEE J. Solid State Circuits, 2018)

13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique. - Hwang Huh; Wanik Cho; Jinhaeng Lee; Yujong Noh; Yongsoon Park; Sunghwa Ok; Jongwoo Kim; Kayoung Cho; Hyunchul Lee; Geonu Kim; Kangwoo Park; Kwanho Kim; et al. (ISSCC, 2020)

A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture. - Jae-Woo Park; Doogon Kim; Sunghwa Ok; Jaebeom Park; Taeheui Kwon; Hyunsoo Lee; Sungmook Lim; Sunyoung Jung; Hyeong-Jin Choi; Taikyu Kang; Gwan Park; Chul-Woo Yang; et al. (ISSCC, 2021)

A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density. - Wanik Cho; Jongseok Jung; Jongwoo Kim; Junghoon Nam; Sangkyu Lee; Yujong Noh; Dauni Kim; Wanseob Lee; Kayoung Cho; Kwanho Kim; Heejoo Lee; Sooyeol Chai; et al. (ISSCC, 2022)

A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $ mathsf{i}$. - Bvunarvul Kim; Seungpil Lee; Beomseok Hah; Kanawoo Park; Yongsoon Park; Kangwook Jo; Yujong Noh; Hyeon-Cheon Seol; Hyunsoo Lee; Jae-Hyeon Shin; Seongjin Choi; Youngdon Jung; et al. (ISSCC, 2023)

A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput. - Wanik Cho; Chanhui Jeong; Jongwoo Kim; Jongseok Jung; Keunseon Ahn; Jayoon Goo; Sangkyu Lee; Kayoung Cho; Tei Cho; Dauni Kim; Gwan Park; Yushin Ahn; et al. (ISSCC, 2025)