Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems. - Hyeji Kim; Injun Choi; Wooseok Byun; Jong-Yeol Lee; Ji-Hoon Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy. - Wooseok Byun; Dokyun Kim; Sung Yeon Kim; Ji-Hoon Kim 003 (A-SSCC, 2019)

High-Speed Visual Target Identification for Low-Cost Wearable Brain-Computer Interfaces. - Dokyun Kim; Wooseok Byun; Yunseo Ku; Ji-Hoon Kim 003 (IEEE Access, 2019)

A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End. - Yongjae Park; Su-Hyun Han 001; Wooseok Byun; Ji-Hoon Kim 003; Hyung-Chul Lee; Seong-Jin Kim (IEEE Trans. Biomed. Circuits Syst., 2020)

A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC. - Wooseok Byun; Minkyu Je; Ji-Hoon Kim 003 (VLSI Circuits, 2021)

An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs. - Wooseok Byun; Minkyu Je; Ji-Hoon Kim 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective. - Wooseok Byun; Minkyu Je; Ji-Hoon Kim 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System. - Minseok Seo; Xuan Truong Nguyen; Seok Joong Hwang; Yongkee Kwon; Guhyun Kim; Chanwook Park; Ilkon Kim; Jaehan Park; Jeongbin Kim 001; Woojae Shin; Jongsoon Won; Haerang Choi; et al. (ASPLOS (3), 2024)

Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers. - Sunyoung Park; Wooseok Byun; Minkyu Je; Ji-Hoon Kim 003 (ISCAS, 2024)