A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter. - WooYoung Jung; HyoungChul Choi; ChangWon Jeong; KwiYoung Kim; WooSeok Kim; HaJun Jeon; GyeSoo Koo; Jihyun Kim 007; JinHo Seo; MyeongLyong Ko; JaeWhui Kim (ISSCC, 2007)

Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. - Dokyung Lim; Sounghun Shin; Seungmin Lee; Kihyun Kwon; Jeongmin An; Wonsik Yu; Chanyoung Jeong; WooSeok Kim; Michael Choi; Jongshin Shin (ISSCC, 2022)

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. - Jusung Lee; Youngwoo Jo; Wonsik Yu; WooSeok Kim; Michael Choi; Sanghune Park; Jongshin Shin (CICC, 2023)