A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface. - Woosong Jung; Jinhyung Lee; Kwangho Lee; Hyojun Kim; Deog-Kyoon Jeong (ISOCC, 2020)

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. - Haram Ju; Kwangho Lee; Woosong Jung; Deog-Kyoon Jeong (A-SSCC, 2021)

A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. - Kwangho Lee; Woosong Jung; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (A-SSCC, 2021)

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. - Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. - Hyojun Kim; Hyeong-Seok Oh; Woosong Jung; Yoonho Song; Jonghyun Oh; Deog-Kyoon Jeong (ISSCC, 2022)

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. - Haram Ju; Kwangho Lee; Kwanseo Park; Woosong Jung; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. - Hyojun Kim; Woosong Jung; Kwandong Kim; Sungwoo Kim 001; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. - Daeho Yun; Eonhui Lee; Woosong Jung; Kahyun Kim; Kyung-Min Beak; Jihee Kim; Hyun Bae Lee; Byeongseon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. - Woosong Jung; Hyojun Kim; Yeonggeun Song; Kwang-Hoon Lee; Deog-Kyoon Jeong (CICC, 2023)

A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector. - Woosong Jung; Minkyo Shim; Seungha Roh; Deog-Kyoon Jeong (ISCAS, 2023)

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. - Woosong Jung; Kwangho Lee; Kwanseo Park; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2023)

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. - Kwang-Hoon Lee; Jung-Hun Park; Yongjae Lee; Yeonggeun Song; Seungha Roh; Minkyo Shim; Yoonho Song; Woosong Jung; Young-Ha Hwang; Jonghyun Oh; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)