An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training. - Wooyoung Jo; Juhyoung Lee; Seunghyun Park; Hoi-Jun Yoo (A-SSCC, 2021)

An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Donghyeon Han; Jinsu Lee; Hoi-Jun Yoo (HCS, 2021)

OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data. - Juhyoung Lee; Sangyeob Kim; Ji-Hoon Kim 004; Sangjin Kim; Wooyoung Jo; Donghyeon Han; Hoi-Jun Yoo (HCS, 2021)

A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Jinsu Lee; Hoi-Jun Yoo (VLSI Circuits, 2021)

OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Donghyeon Han; Jinsu Lee; Hoi-Jun Yoo (VLSI Circuits, 2021)

GST: Group-Sparse Training for Accelerating Deep Reinforcement Learning. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Hoi-Jun Yoo (CoRR, 2021)

Low-power Autonomous Adaptation System with Deep Reinforcement Learning. - Juhyoung Lee; Wooyoung Jo; Seong-Wook Park; Hoi-Jun Yoo (AICAS, 2022)

A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks. - Wooyoung Jo; Sangjin Kim; Juhyeong Lee; Soyeon Um; Zhiyong Li 016; Hoi-Jun Yoo (ISCAS, 2022)

OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Ji-Hoon Kim 004; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2022)

ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Hoi-Jun Yoo (IEEE Micro, 2022)

TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning. - Sangyeob Kim; Juhyoung Lee; Sanghoon Kang; Donghyeon Han; Wooyoung Jo; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture. - Jiwon Choi; Sangyeob Kim; Wonhoon Park; Wooyoung Jo; Hoi-Jun Yoo (A-SSCC, 2023)

An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision. - Jingu Lee; Sangjin Kim; Wooyoung Jo; Hoi-Jun Yoo (A-SSCC, 2023)

A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC. - Seongyon Hong; Soyeon Um; Sangjin Kim; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency. - Seryeong Kim; Soyeon Kim; Soyeon Um; Sangjin Kim; Zhiyong Li 016; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

A 15.9 mW 96.5 fps Memory-Efficient 3D Reconstruction Processor with Dilation-based TSDF Fusion and Block-Projection Cache System. - Hankyul Kwon; Gwangtae Park; Junha Ryu; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration. - Wonhoon Park; Junha Ryu; Sangjin Kim; Soyeon Um; Wooyoung Jo; Sangyoeb Kim; Hoi-Jun Yoo (ISCAS, 2023)

DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (ISSCC, 2023)

NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices. - Wooyoung Jo; Sangjin Kim; Juhyoung Lee; Donghyeon Han; Sangyeob Kim; Seungyoon Choi; Hoi-Jun Yoo (VLSI Technology and Circuits, 2023)

Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (VLSI Technology and Circuits, 2023)

A 66.6 FPS High Quality Gaussian Splats Rendering FPGA Processor with Reconfigurable Computation Architecture. - Hongseok Lee; Gwangtae Park; Wonhoon Park; Wooyoung Jo; Jongjun Park; Hoi-Jun Yoo (A-SSCC, 2024)

NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Sangyeob Kim; Hoi-Jun Yoo (COOL CHIPS, 2024)

A Low-Power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-Device AI. - Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Soyeon Kim; Seongyon Hong; Nayeong Lee; Hoi-Jun Yoo (HCS, 2024)

A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision. - Jiwon Choi; Wooyoung Jo; Seongyon Hong; Beomseok Kwon; Wonhoon Park; Hoi-Jun Yoo (ISCAS, 2024)

20.5 C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models. - Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Soyeon Kim; Seongyon Hong; Hoi-Jun Yoo (ISSCC, 2024)

Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow. - Seongyon Hong; Wooyoung Jo; Sangjin Kim; Sangyeob Kim; Kyomin Sohn; Hoi-Jun Yoo (VLSI Technology and Circuits, 2024)

DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 92 fps and 2.56 mJ/Frame Computing-In-Memory-Based Human Pose Estimation Accelerator With Resource-Efficient Macro for Mobile Devices. - Beomseok Kwon; Zhiyong Li 016; Sangjin Kim; Wooyoung Jo; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 32.65µm2 Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array. - Jingu Lee; Sangwoo Ha; Sunjoo Whang; Soyeon Kim; Sangjin Kim; Soyeon Um; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2025)

A 17.1 TOPS/W FP-INT Transformer Inference Accelerator with Sparsity Boosting and Output Importance-Aware Processing. - Jeonggyu So; Seongyon Hong; Jiwon Choi; Wooyoung Jo; Sangjin Kim; Hoi-Jun Yoo; Donghyeon Han (ISCAS, 2025)

23.7 BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Grouping. - Wooyoung Jo; Seongyon Hong; Jiwon Choi; Beomseok Kwon; Haoyang Sang; Dongseok Im; Sangyeob Kim; Sangjin Kim; Taekwon Lee; Hoi-Jun Yoo (ISSCC, 2025)

Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI. - Seongyon Hong; Wooyoung Jo; Sangjin Kim; Sangyeob Kim; Soyeon Um; Kyomin Sohn; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2025)

MedErr-CT: A Visual Question Answering Benchmark for Identifying and Correcting Errors in CT Reports. - Sunggu Kyung; Hyungbin Park; Jinyoung Seo; Jimin Sung; Jihyun Kim; Dongyeong Kim; Wooyoung Jo; Yoojin Nam; Sangah Park; Taehee Kwon 003; Sang Min Lee; Namkug Kim (CoRR, 2025)

MedRegion-CT: Region-Focused Multimodal LLM for Comprehensive 3D CT Report Generation. - Sunggu Kyung; Jinyoung Seo; Hyunseok Lim; Dongyeong Kim; Hyungbin Park; Jimin Sung; Jihyun Kim; Wooyoung Jo; Yoojin Nam; Namkug Kim (CoRR, 2025)