Multiple-Fault Detection in Iterative Logic Arrays. - Wu-Tung Cheng; Janak H. Patel (ITC, 1985)

Testing and Error Detection in Iterative Logic Arrays - Wu-Tung Cheng (1985)

A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. - Wu-Tung Cheng; Janak H. Patel (IEEE Trans. Computers, 1987)

Split Circuit Model for Test Generation. - Wu-Tung Cheng (DAC, 1988)

The BACK algorithm for sequential test generation. - Wu-Tung Cheng (ICCD, 1988)

Differential Fault Simulation - a Fast Method Using Minimal Memory. - Wu-Tung Cheng; Meng-Lin Yu (DAC, 1989)

Gentest: An Automatic Test-Generation System for Sequential Circuits. - Wu-Tung Cheng; Tapan J. Chakraborty (Computer, 1989)

PROOFS: a super fast fault simulator for sequential circuits. - Wu-Tung Cheng; Janak H. Patel (EURO-DAC, 1990)

Diagnosis for wiring interconnects. - Wu-Tung Cheng; James L. Lewandowski; Eleanor Wu (ITC, 1990)

Differential fault simulation for sequential circuits. - Wu-Tung Cheng; Meng-Lin Yu (J. Electron. Test., 1990)

Optimal diagnostic methods for wiring interconnects. - Wu-Tung Cheng; James L. Lewandowski; Eleanor Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

PROOFS: a fast, memory-efficient sequential circuit fault simulator. - Thomas M. Niermann; Wu-Tung Cheng; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A Universal Technique for Accelerating Simulation of Scan Test Patterns. - Bejoy G. Oomman; Wu-Tung Cheng; John A. Waicukauski (ITC, 1996)

High time for high level ATPG. - Wu-Tung Cheng (ITC, 1999)

Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. - Wu-Tung Cheng (Asian Test Symposium, 2000)

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. - Xijiang Lin; Wu-Tung Cheng; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2000)

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (Asian Test Symposium, 2001)

Effect of RTL coding style on testability. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherhee; Wu-Tung Cheng; Sudhakar M. Reddy (CICC, 2001)

On RTL scan design. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Dan Devries; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2001)

Core - Clustering Based SOC Test Scheduling Optimization. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng (Asian Test Symposium, 2002)

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng; Paul Reuter; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan (ITC, 2002)

Constraint Driven Pin Mapping for Concurrent SOC Testing. - Yu Huang 005; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan; Yanping Zhang; Wu-Tung Cheng; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

On Concurrent Test of Core-Based SOC Design. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (J. Electron. Test., 2002)

Synthesis of Scan Chains for Netlist Descriptions at RT-Level. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Wu-Tung Cheng; Sudhakar M. Reddy (J. Electron. Test., 2002)

Testing Delay Faults in Embedded CAMs. - Xiaogang Du; Sudhakar M. Reddy; Joseph Rayhawk; Wu-Tung Cheng (Asian Test Symposium, 2003)

Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. - Yu Huang 005; Wu-Tung Cheng; Cheng-Ju Hsieh; Huan-Yung Tseng; Alou Huang; Yu-Ting Hung (Asian Test Symposium, 2003)

Using embedded infrastructure IP for SOC post-silicon verification. - Yu Huang 005; Wu-Tung Cheng (DAC, 2003)

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Sudhakar M. Reddy (ISQED, 2003)

Silicon Diagnosis. - Wu-Tung Cheng (ITC, 2003)

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. - Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Cheng-Ju Hsieh; Yu-Ting Hung (ITC, 2003)

BIST for Deep Submicron ASIC Memories with High Performance Application. - Theo J. Powell; Wu-Tung Cheng; Joseph Rayhawk; Omer Samman; Paul Policke; Sherry Lai (ITC, 2003)

Compactor Independent Direct Diagnosis. - Wu-Tung Cheng; Kun-Han Tsai; Yu Huang 005; Nagesh Tamarapalli; Janusz Rajski (Asian Test Symposium, 2004)

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. - Yu Huang 005; Wu-Tung Cheng; Cheng-Ju Hsieh; Huan-Yung Tseng; Alou Huang; Yu-Ting Hung (DATE, 2004)

Logic BIST with Scan Chain Segmentation. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ITC, 2004)

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. - Xiaogang Du; Sudhakar M. Reddy; Wu-Tung Cheng; Joseph Rayhawk; Nilanjan Mukherjee 001 (VLSI Design, 2004)

Memory BIST Using ESP. - Xiaogang Du; Sudhakar M. Reddy; Don E. Ross; Wu-Tung Cheng; Joseph Rayhawk (VTS, 2004)

Logic BIST Using Constrained Scan Cells. - Liyang Lai; Thomas Rinderknecht; Wu-Tung Cheng; Janak H. Patel (VTS, 2004)

Using fault model relaxation to diagnose real scan chain defects. - Yu Huang 005; Wu-Tung Cheng; Greg Crowell (ASP-DAC, 2005)

Achieving High Test Quality with Reduced Pin Count Testing. - Jay Jahangiri; Nilanjan Mukherjee 001; Wu-Tung Cheng; Subramanian Mahadevan; Ron Press (Asian Test Symposium, 2005)

Bridge Defect Diagnosis with Physical Information. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy (Asian Test Symposium, 2005)

Hardware Ef.cient LBISTWith Complementary Weights. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ICCD, 2005)

Full-speed field-programmable memory BIST architecture. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2005)

Compressed pattern diagnosis for scan chain failures. - Yu Huang 005; Wu-Tung Cheng; Janusz Rajski (ITC, 2005)

Compression mode diagnosis enables high volume monitoring diagnosis flow. - Andreas Leininger; Peter Muhmenthaler; Wu-Tung Cheng; Nagesh Tamarapalli; Wu Yang; Kun-Han Hans Tsai (ITC, 2005)

X-filter: filtering unknowns from compacted test responses. - Manish Sharma; Wu-Tung Cheng (ITC, 2005)

Full-speed field programmable memory BIST supporting multi-level looping. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (MTDT, 2005)

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. - Xiaogang Du; Nilanjan Mukherjee 001; Chris Hill; Wu-Tung Cheng; Sudhakar M. Reddy (ATS, 2006)

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. - Andreas Leininger; Ajay Khoche; Martin Fischer 002; Nagesh Tamarapalli; Wu-Tung Cheng; Randy Klingenberg; Wu Yang (ATS, 2006)

Interconnect Open Defect Diagnosis with Physical Information. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy (ATS, 2006)

Signature Based Diagnosis for Logic BIST. - Wu-Tung Cheng; Manish Sharma; Thomas Rinderknecht; Liyang Lai; Chris Hill (ITC, 2006)

Diagnosis with Limited Failure Information. - Yu Huang 005; Wu-Tung Cheng; Nagesh Tamarapalli; Janusz Rajski; Randy Klingenberg; Will Hsu; Yuan-Shih Chen (ITC, 2006)

X-Press Compactor for 1000x Reduction of Test Data. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2006)

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. - Nandu Tendolkar; Dawit Belete; Bill Schwarz; Bob Podnar; Akshay Gupta; Steve Karako; Wu-Tung Cheng; Alex Babin; Kun-Han Tsai; Nagesh Tamarapalli; Greg Aldrich (ITC, 2006)

On Methods to Improve Location Based Logic Diagnosis. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy; Huaxing Tang (VLSI Design, 2006)

Fault Dictionary Based Scan Chain Failure Diagnosis. - Ruifeng Guo; Yu Huang 005; Wu-Tung Cheng (ATS, 2007)

A RTL Testability Analyzer Based on Logical Virtual Prototyping. - Yu Huang 005; Nilanjan Mukherjee 001; Wu-Tung Cheng; Greg Aldrich (ATS, 2007)

Programmable Scan-Based Logic Built-In Self Test. - Liyang Lai; Wu-Tung Cheng; Thomas Rinderknecht (ATS, 2007)

Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead. - Huaxing Tang; Chen Liu; Wu-Tung Cheng; Sudahkar M. Reddy; Wei Zou (ATS, 2007)

Scan Diagnosis and Its Successful Industrial Applications. - Wu Yang; Wu-Tung Cheng; Yu Huang 005; Martin Keim; Randy Klingenberg (ATS, 2007)

A complete test set to diagnose scan chain failures. - Ruifeng Guo; Yu Huang 005; Wu-Tung Cheng (ITC, 2007)

Diagnose compound scan chain and system logic defects. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Will Hsu; Yuan-Shih Chen; Albert Mann (ITC, 2007)

Interconnect open defect diagnosis with minimal physical information. - Chen Liu; Wei Zou; Sudhakar M. Reddy; Wu-Tung Cheng; Manish Sharma; Huaxing Tang (ITC, 2007)

Faster defect localization in nanometer technology based on defective cell diagnosis. - Manish Sharma; Wu-Tung Cheng; Ting-Pu Tai; Y. S. Cheng; Will Hsu; Chen Liu; Sudhakar M. Reddy; Albert Mann (ITC, 2007)

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy; Huaxing Tang (VTS, 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Enhancing Transition Fault Model for Delay Defect Diagnosis. - Wu-Tung Cheng; Brady Benware; Ruifeng Guo; Kun-Han Tsai; Takeo Kobayashi; Kazuyuki Maruo; Michinobu Nakao; Yoshiaki Fukui; Hideyuki Otake (ATS, 2008)

Hyperactive Faults Dictionary to Increase Diagnosis Throughput. - Chen Liu; Wu-Tung Cheng; Huaxing Tang; Sudhakar M. Reddy; Wei Zou; Manish Sharma (ATS, 2008)

A Robust Automated Scan Pattern Mismatch Debugger. - Kun-Han Tsai; Ruifeng Guo; Wu-Tung Cheng (ATS, 2008)

Diagnose Multiple Stuck-at Scan Chain Faults. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo (ETS, 2008)

Detection and Diagnosis of Static Scan Cell Internal Defect. - Ruifeng Guo; Liyang Lai; Yu Huang 005; Wu-Tung Cheng (ITC, 2008)

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. - Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker 001; Martin Keim; Wu-Tung Cheng (ITC, 2008)

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. - Manish Sharma; Brady Benware; Lei Ling; David Abercrombie; Lincoln Lee; Martin Keim; Huaxing Tang; Wu-Tung Cheng; Ting-Pu Tai; Yi-Jung Chang; Reinhart Lin; Albert Mann (ITC, 2008)

Reducing Scan Shift Power at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (VTS, 2008)

Automatic Test Pattern Generation for Interconnect Open Defects. - Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker 001; Martin Keim; Wu-Tung Cheng (VTS, 2008)

Survey of Scan Chain Diagnosis. - Yu Huang 005; Ruifeng Guo; Wu-Tung Cheng; James Chien-Mo Li (IEEE Des. Test Comput., 2008)

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (Asian Test Symposium, 2009)

On Improving Diagnostic Test Generation for Scan Chain Failures. - Xun Tang; Ruifeng Guo; Wu-Tung Cheng; Sudhakar M. Reddy; Yu Huang 005 (Asian Test Symposium, 2009)

At-Speed Scan Test Method for the Timing Optimization and Calibration. - Kun-Han Tsai; Ruifeng Guo; Wu-Tung Cheng (Asian Test Symposium, 2009)

Improving compressed test pattern generation for multiple scan chain failure diagnosis. - Xun Tang; Ruifeng Guo; Wu-Tung Cheng; Sudhakar M. Reddy (DATE, 2009)

Speed-Path Debug Using At-Speed Scan Test Patterns. - Ruifeng Guo; Wu-Tung Cheng; Kun-Han Tsai (ETS, 2009)

Emulating and diagnosing IR-drop by using dynamic SDF. - Ke Peng; Yu Huang 005; Ruifeng Guo; Wu-Tung Cheng; Mohammad Tehranipoor (ASP-DAC, 2010)

Improved weight assignment for logic switching activity during at-speed test pattern generation. - Meng-Fan Wu; Hsin-Cheih Pan; Teng-Han Wang; Jiun-Lang Huang; Kun-Han Tsai; Wu-Tung Cheng (ASP-DAC, 2010)

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. - Wu-Tung Cheng; Yu Huang 005 (Asian Test Symposium, 2010)

Diagnosis of Multiple Physical Defects Using Logic Fault Models. - Xun Tang; Wu-Tung Cheng; Ruifeng Guo; Sudhakar M. Reddy (Asian Test Symposium, 2010)

Full-circuit SPICE simulation based validation of dynamic delay estimation. - Ke Peng; Yu Huang 005; Pinki Mallick; Wu-Tung Cheng; Mohammad Tehranipoor (ETS, 2010)

Scan based speed-path debug for a microprocessor. - Jing Zeng; Ruifeng Guo; Wu-Tung Cheng; Michael Mateja; Jing Wang; Kun-Han Tsai; Ken Amstutz (ETS, 2010)

A scalable quantitative measure of IR-drop effects for scan pattern generation. - Meng-Fan Wu; Kun-Han Tsai; Wu-Tung Cheng; Hsin-Cheih Pan; Jiun-Lang Huang; Augusli Kifli (ICCAD, 2010)

Case study of scan chain diagnosis and PFA on a low yield wafer. - Yu Huang 005; Brady Benware; Wu-Tung Cheng; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (ITC, 2010)

Test cycle power optimization for scan-based designs. - Kun-Han Tsai; Yu Huang 005; Wu-Tung Cheng; Ting-Pu Tai; Augusli Kifli (ITC, 2010)

On Reducing Scan Shift Activity at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Using Design Partitioning to Reduce Diagnosis Memory Footprint. - Xiaoxin Fan; Huaxing Tang; Sudhakar M. Reddy; Wu-Tung Cheng; Brady Benware (Asian Test Symposium, 2011)

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. - Xun Tang; Wu-Tung Cheng; Ruifeng Guo; Huaxing Tang; Sudhakar M. Reddy (DFT, 2011)

Deterministic IDDQ diagnosis using a net activation based model. - Andras Kun; Ralf Arnold; Peter Heinrich; Gwenolé Maugard; Huaxing Tang; Wu-Tung Cheng (ITC, 2011)

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. - Manish Sharma; Avijit Dutta; Wu-Tung Cheng; Brady Benware; Mark Kassab (ITC, 2011)

Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis. - Wu-Tung Cheng; Feng-Ming Kuo (Asian Test Symposium, 2012)

Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. - Xiaoxin Fan; Manish Sharma; Wu-Tung Cheng; Sudhakar M. Reddy (Asian Test Symposium, 2012)

A Hybrid Flow for Memory Failure Bitmap Classification. - Jianbo Li; Yu Huang 005; Wu-Tung Cheng; Chris Schuermyer; Dong Xiang; Eric Faehn; Ruth Farrugia (Asian Test Symposium, 2012)

Programmable Leakage Test and Binning for TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (Asian Test Symposium, 2012)

Small delay testing for TSVs in 3-D ICs. - Shi-Yu Huang; Yu-Hsiang Lin; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (DAC, 2012)

Improved volume diagnosis throughput using dynamic design partitioning. - Xiaoxin Fan; Huaxing Tang; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Brady Benware (ITC, 2012)

A unified method for parametric fault characterization of post-bond TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (ITC, 2012)

Scan-Based Speed-Path Debug for a Microprocessor. - Jing Zeng; Ruifeng Guo; Wu-Tung Cheng; Michael Mateja; Jing Wang (IEEE Des. Test Comput., 2012)

Mid-bond Interposer Wire Test. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (Asian Test Symposium, 2013)

At-speed BIST for interposer wires supporting on-the-spot diagnosis. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IOLTS, 2013)

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. - Shi-Yu Huang; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2013)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

Improve speed path identification with suspect path expressions. - Jiun-Lang Huang; Kun-Han Tsai; Yu-Ping Liu; Ruifeng Guo; Manish Sharma; Wu-Tung Cheng (VLSI-DAT, 2013)

Distributed dynamic partitioning based diagnosis of scan chain. - Yu Huang 005; Xiaoxin Fan; Huaxing Tang; Manish Sharma; Wu-Tung Cheng; Brady Benware; Sudhakar M. Reddy (VTS, 2013)

Oscillation-Based Prebond TSV Test. - Li-Ren Huang; Shi-Yu Huang; Stephen K. Sunter; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. - Shi-Yu Huang; Yu-Hsiang Lin; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. - Shi-Yu Huang; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ATS, 2014)

Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models. - Huaxing Tang; Brady Benware; Michael Reese; Joseph Caroselli; Thomas Herrmann; Friedrich Hapke; Robert Tao; Wu-Tung Cheng; Manish Sharma (ATS, 2014)

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. - Shi-Yu Huang; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2014)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Diagnose Failures Caused by Multiple Locations at a Time. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001; Wu-Tung Cheng; Yu Huang 005; Huaxing Tang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. - Xijiang Lin; Wu-Tung Cheng; Janusz Rajski (ATS, 2015)

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Hans Tsai; Wu-Tung Cheng (DATE, 2015)

Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. - Yu Huang 005; Wu Yang; Wu-Tung Cheng (ETS, 2015)

Monitoring the delay of long interconnects via distributed TDC. - Meng-Ting Tsai; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2015)

Identify problematic layout patterns through volume diagnosis. - Wu-Tung Cheng (VLSI-DAT, 2015)

A test-application-count based learning technique for test time reduction. - Guo-Yu Lin; Kun-Han Tsai; Jiun-Lang Huang; Wu-Tung Cheng (VLSI-DAT, 2015)

Diagnosing timing related cell internal defects for FinFET technology. - Huaxing Tang; Ting-Pu Tai; Wu-Tung Cheng; Brady Benware; Friedrich Hapke (VLSI-DAT, 2015)

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. - Wu-Tung Cheng; Sudhakar M. Reddy (VLSID, 2015)

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. - Xijiang Lin; Sudhakar M. Reddy; Wu-Tung Cheng (ATS, 2016)

Testing of small delay faults in a clock network. - Shaofu Yang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2016)

A wide-range clock signal generation scheme for speed grading of a logic core. - Shi-Yu Huang; Tzu-Heng Huang; Kun-Han Tsai; Wu-Tung Cheng (HPCS, 2016)

Online slack-time binning for IO-registered die-to-die interconnects. - Chih-Chieh Zheng; Shi-Yu Huang; Shyue-Kung Lu; Ting-Chi Wang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2016)

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. - Shi-Yu Huang; Chih-Chieh Cheng; Meng-Ting Tsai; Kuan-Chen Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. - Wu-Tung Cheng; Randy Klingenberg; Brady Benware; Wu Yang; Manish Sharma; Geir Eide; Yue Tian; Sudhakar M. Reddy; Yan Pan; Sherwin Fernandes; Atul Chittora (ATS, 2017)

Scan Chain Diagnosis Based on Unsupervised Machine Learning. - Yu Huang 005; Brady Benware; Randy Klingenberg; Huaxing Tang; Jayant Dsouza; Wu-Tung Cheng (ATS, 2017)

Volume diagnosis data mining. - Wu-Tung Cheng; Yue Tian; Sudhakar M. Reddy (ETS, 2017)

On designing two-dimensional scan architecture for test chips. - Yu Huang 005; Wu-Tung Cheng (VLSI-DAT, 2017)

Circuit and Methodology for Testing Small Delay Faults in the Clock Network. - Shaofu Yang; Zhi-Yuan Wen; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Hans Tsai; Wu-Tung Cheng (ASP-DAC, 2019)

TEA: A Test Generation Algorithm for Designs with Timing Exceptions. - Naixing Wang; Chen Wang 014; Kun-Han Tsai; Wu-Tung Cheng; Xijiang Lin; Mark Kassab; Irith Pomeranz (ATS, 2019)

Deep Learning Based Test Compression Analyzer. - Cheng-Hung Wu; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Gaurav Veda; Sudhakar M. Reddy; Chun-Cheng Hu; Chong-Siao Ye (ATS, 2019)

A supervised machine learning application in volume diagnosis. - Yue Tian; Gaurav Veda; Wu-Tung Cheng; Manish Sharma; Huaxing Tang; Neerja Bawaskar; Sudhakar M. Reddy (ETS, 2019)

Reversible Scan Based Diagnostic Patterns. - Yu Huang 005; Szczepan Urban; Wu-Tung Cheng; Manish Sharma; Fengju Niu; Junna Zhong; Wen-Lung Hsu (VLSI-DAT, 2019)

On Cyclic Scan Integrity Tests for EDT-based Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (VTS, 2019)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. - Liyang Lai; Qiting Zhang; Kun-Han Hans Tsai; Wu-Tung Cheng (ITC-Asia, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Scan Integrity Tests for EDT Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Des. Test, 2020)

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. - Xijiang Lin; Wu-Tung Cheng; Takeo Kobayashi; Andreas Glowatz (ATS, 2021)

Diagnosis and Yield Learning. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Sameer Chillarige (ITC-Asia, 2021)

Autonomous Scan Patterns for Laser Voltage Imaging. - Wu-Tung Cheng; Sylwester Milewski; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Trans. Emerg. Top. Comput., 2021)

Industry Evaluation of Reversible Scan Chain Diagnosis. - Soumya Mittal; Szczepan Urban; Kun Young Chung; Jakub Janicki; Wu-Tung Cheng; Martin Parley; Manish Sharma; Shaun Nicholson (ITC, 2022)

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. - Shi-Xuan Zheng; Chung-Yu Yeh; Kuen-Jong Lee; Chen Wang 014; Wu-Tung Cheng; Mark Kassab; Janusz Rajski; Sudhakar M. Reddy (VTS, 2022)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage. - Wu-Tung Cheng; Manish Sharma; Xin Yang; Artur Stelmach; Szczepan Urban; Jakub Janicki; Preston McWithey (ITC, 2024)

APT: Optimal Tree for Diagnosis Simulation. - Wu-Tung Cheng (VTS, 2025)

Innovation Practices Track: Frontiers in Diagnosis and Debug. - Suriyaprakash Natarajan; Saghir A. Shaikh; Wu-Tung Cheng; Sankaran Menon (VTS, 2025)