A 4-Kb low power 4-T SRAM design with negative word-line gate drive. - Chua-Chin Wang; Ching-Li Lee; Wun-Ji Lin (ISCAS, 2006)

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. - Chua-Chin Wang; Jian-Ming Huang; Yih-Long Tseng; Wun-Ji Lin; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme. - Chua-Chin Wang; Ching-Li Lee; Wun-Ji Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. - Chua-Chin Wang; Gang-Neng Sung; Chi-Chun Huang; Ching-Li Lee; Tian-Hau Chen; Wun-Ji Lin; Ron Hu (J. Circuits Syst. Comput., 2008)