A fast fault simulation algorithm for combinational circuits. - Wuudiann Ke; Sharad C. Seth; Bhargab B. Bhattacharya (ICCAD, 1988)

Synthesis of Delay-Verifiable Two-Level Circuits. - Wuudiann Ke; Premachandran R. Menon (EDAC-ETC-EUROASIC, 1994)

Delay-Verifiability of Combinational Circuits Based on Primitive Faults. - Wuudiann Ke; Premachandran R. Menon (ICCD, 1994)

Realization of fully path-delay-fault testable non-scan sequential circuits. - Wuudiann Ke; Premachandran R. Menon (VTS, 1994)

A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. - Wuudiann Ke; Duy Le; Najmi T. Jarwala (ITC, 1995)

Multifault testability of delay-testable circuits. - Wuudiann Ke; Premachandran R. Menon (VTS, 1995)

Multifault and delay-fault testability of multilevel circuits. - Wuudiann Ke; Premachandran R. Menon (J. Electron. Test., 1995)

Synthesis of Delay-Verifiable Combinational Circuits. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Computers, 1995)

Path-delay-fault testable nonscan sequential circuits. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Delay-testable implementations of symmetric functions. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Hybrid Pin Control Using Boundary-Scan And Its Applications. - Wuudiann Ke (Asian Test Symposium, 1996)

Backplane Interconnect Test in a Boundary-Scan Environment. - Wuudiann Ke (ITC, 1996)