A design technique overview on broadband RF ESD protection circuit designs. - Li Wang 058; Rui Ma 003; Albert Z. Wang; Xin Wang 031; Bin Zhao 002; X. Shawn Wang; Patrick Yue; Zitao Shi; Yuhua Cheng (MWSCAS, 2012)

A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design. - X. Shawn Wang; Xin Wang 031; Fei Lu 004; Li Wang 058; Rui Ma 003; Zongyu Dong; Li Sun; Albert Z. Wang; C. Patrick Yue; Dawn Wang; Alvin J. Joseph (CICC, 2013)

Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection. - X. Shawn Wang; Xin Wang 031; Fei Lu 004; Chen Zhang 017; Zongyu Dong; Li Wang 058; Rui Ma 003; Zitao Shi; Albert Z. Wang; Mau-Chung Frank Chang; Dawn Wang; Alvin J. Joseph; et al. (IEEE J. Solid State Circuits, 2014)

A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS. - Fei Lu 004; Rui Ma 003; Zongyu Dong; Li Wang 058; Chen Zhang 017; Chenkun Wang; Qi Chen 008; X. Shawn Wang; Feilong Zhang 001; Cheng Li; He Tang; Yuhua Cheng; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

More-Than-Moore: 3D heterogeneous integration into CMOS technologies. - Albert Z. Wang; Qi Chen 008; Cheng Li; Fei Lu 004; Chenkun Wang; Feilong Zhang 001; X. Shawn Wang; Jimmy Ng; Ya-Hong Xie; Rui Ma 003; Li Wang 058; Lin Lin 011 (NEMS, 2017)

Intelligent plankton image classification with deep learning. - Hussein A. Al-Barazanchi; Abhishek Verma; X. Shawn Wang (Int. J. Comput. Vis. Robotics, 2018)

A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. - X. Shawn Wang; Xin Jin; Jieqiong Du; Yilei Li; Yuan Du; Chien-Heng Wong; Yen-Cheng Kuan; Chi-Hang Chan; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). - Yuan Du; Li Du; Xuefeng Gu; Jieqiong Du; X. Shawn Wang; Boyu Hu; Mingzhe Jiang; Xiaoliang Chen; Subramanian S. Iyer; Mau-Chung Frank Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. - Feilong Zhang 001; Chenkun Wang; Fei Lu 004; Qi Chen 008; Cheng Li; X. Shawn Wang; Daguang Li; Albert Z. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)