On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. - Florence Azaïs; Serge Bernard; Yves Bertrand; Xavier Michel; Michel Renovell (LATW, 2001)

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. - Florence Azaïs; Serge Bernard; Yves Bertrand; Xavier Michel; Michel Renovell (VTS, 2001)

Gate speed improvement at minimal power dissipation. - Philippe Maurine; Xavier Michel; Nadine Azémard; Daniel Auvergne (APCCAS (2), 2002)

Metric Definition for Circuit Speed Optimization. - Xavier Michel; Alexandre Verle; Nadine Azémard; Philippe Maurine; Daniel Auvergne (PATMOS, 2003)

CMOS Gate Sizing under Delay Constraint. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2003)

Delay bound based CMOS gate sizing technique. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ISCAS (5), 2004)

Performance Metric Based Optimization Protocol. - Xavier Michel; Alexandre Verle; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Low Power Oriented CMOS Circuit Optimization Protocol. - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (DATE, 2005)

A Haptic Knob with a Hybrid Ultrasonic Motor and Powder Clutch Actuator. - Dominique Chapuis; Xavier Michel; Roger Gassert; Chee-Meng Chew; Etienne Burdet; Hannes Bleuler (WHC, 2007)