A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). - Xavier Vera; Josep Llosa; Antonio González 001; Nerina Bermudo (Euro-Par, 2000)

An efficient solver for Cache Miss Equations. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (ISPASS, 2000)

Optimizing cache miss equations polyhedra. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (SIGARCH Comput. Archit. News, 2000)

Let's Study Whole-Program Cache Behaviour Analytically. - Xavier Vera; Jingling Xue (HPCA, 2002)

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. - Jaume Abella 001; Antonio González 001; Josep Llosa; Xavier Vera (ICPP Workshops, 2002)

Near-Optimal Padding for Removing Conflict Misses. - Xavier Vera; Josep Llosa; Antonio González 001 (LCPC, 2002)

Optimizing Program Locality Through CMEs and GAs. - Xavier Vera; Jaume Abella 001; Antonio González 001; Josep Llosa (IEEE PACT, 2003)

Code Tiling for Improving the Cache Performance of PDE Solvers. - Qingguang Huang; Jingling Xue; Xavier Vera (ICPP, 2003)

Data Caches in Multitasking Hard Real-Time Systems. - Xavier Vera; Björn Lisper; Jingling Xue (RTSS, 2003)

Data cache locking for higher program predictability. - Xavier Vera; Björn Lisper; Jingling Xue (SIGMETRICS, 2003)

Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. - Jingling Xue; Xavier Vera (IEEE Trans. Computers, 2004)

A fast and accurate framework to analyze and optimize cache memory behavior. - Xavier Vera; Nerina Bermudo; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2004)

Variable-Based Multi-module Data Caches for Clustered VLIW Processors. - Enric Gibert; Jaume Abella 001; F. Jesús Sánchez; Xavier Vera; Antonio González 001 (IEEE PACT, 2005)

IATAC: a smart predictor to turn-off L2 cache lines. - Jaume Abella 001; Antonio González 001; Xavier Vera; Michael F. P. O'Boyle (ACM Trans. Archit. Code Optim., 2005)

An accurate cost model for guiding data locality transformations. - Xavier Vera; Jaume Abella 001; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2005)

Empowering a helper cluster through data-width aware instruction selection policies. - Osman S. Unsal; Oguz Ergin; Xavier Vera; Antonio González 001 (IPDPS, 2006)

Exploiting Narrow Values for Soft Error Tolerance. - Oguz Ergin; Osman S. Unsal; Xavier Vera; Antonio González 001 (IEEE Comput. Archit. Lett., 2006)

Impact of Parameter Variations on Circuits and Microarchitecture. - Osman S. Unsal; James W. Tschanz; Keith A. Bowman; Vivek De; Xavier Vera; Antonio González 001; Oguz Ergin (IEEE Micro, 2006)

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. - Jaume Abella 001; Xavier Vera; Osman S. Unsal; Oguz Ergin; Antonio González 001 (IOLTS, 2007)

Surviving to Errors in Multi-Core Environments. - Xavier Vera; Jaume Abella 001 (IOLTS, 2007)

Penelope: The NBTI-Aware Processor. - Jaume Abella 001; Xavier Vera; Antonio González 001 (MICRO, 2007)

Data cache locking for tight timing calculations. - Xavier Vera; Björn Lisper; Jingling Xue (ACM Trans. Embed. Comput. Syst., 2007)

Issue system protection mechanisms. - Pedro Chaparro; Jaume Abella 001; Javier Carretero; Xavier Vera (ICCD, 2008)

On-Line Failure Detection and Confinement in Caches. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (IOLTS, 2008)

On-line Failure Detection in Memory Order Buffers. - Javier Carretero; Xavier Vera; Pedro Chaparro; Jaume Abella 001 (ITC, 2008)

Refueling: Preventing Wire Degradation due to Electromigration. - Jaume Abella 001; Xavier Vera; Osman S. Unsal; Oguz Ergin; Antonio González 001; James W. Tschanz (IEEE Micro, 2008)

DFx for massively multiprocessors. - Xavier Vera (IOLTS, 2009)

Online error detection and correction of erratic bits in register files. - Xavier Vera; Jaume Abella 001; Javier Carretero; Pedro Chaparro; Antonio González 001 (IOLTS, 2009)

End-to-end register data-flow continuous self-test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (ISCA, 2009)

Low Vccmin fault-tolerant cache with highly predictable performance. - Jaume Abella 001; Javier Carretero; Pedro Chaparro; Xavier Vera; Antonio González 001 (MICRO, 2009)

Reducing Soft Errors through Operand Width Aware Policies. - Oguz Ergin; Osman S. Unsal; Xavier Vera; Antonio González 001 (IEEE Trans. Dependable Secur. Comput., 2009)

Selective replication: A lightweight technique for soft errors. - Xavier Vera; Jaume Abella 001; Javier Carretero; Antonio González 001 (ACM Trans. Comput. Syst., 2009)

The split register file. - Jaume Abella 001; Javier Carretero; Pedro Chaparro; Xavier Vera (DATE, 2010)

High-Performance low-vcc in-order core. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (HPCA, 2010)

MT-SBST: Self-test optimization in multithreaded multicore architectures. - Nikos Foutris; Mihalis Psarakis; Dimitris Gizopoulos; Andreas Apostolakis; Xavier Vera; Antonio González 001 (ITC, 2010)

VCTA: A Via-Configurable Transistor Array regular fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (VLSI-SoC, 2010)

Electromigration for microarchitects. - Jaume Abella 001; Xavier Vera (ACM Comput. Surv., 2010)

Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. - Javier Carretero; Xavier Vera; Pedro Chaparro; Jaume Abella 001 (IEEE Trans. Computers, 2010)

Architectures for online error detection and recovery in multicore processors. - Dimitris Gizopoulos; Mihalis Psarakis; Sarita V. Adve; Pradeep Ramachandran; Siva Kumar Sastry Hari; Daniel J. Sorin; Albert Meixner; Arijit Biswas; Xavier Vera (DATE, 2011)

Control-Flow Recovery Validation Using Microarchitectural Invariants. - Javier Carretero; Jaume Abella 001; Xavier Vera; Pedro Chaparro (DFT, 2011)

Hardware/software-based diagnosis of load-store queues using expandable activity logs. - Javier Carretero; Xavier Vera; Jaume Abella 001; Tanausú Ramírez; Matteo Monchiero; Antonio González 001 (HPCA, 2011)

New reliability mechanisms in memory design for sub-22nm technologies. - Nivard Aymerich; A. Asenov; Andrew R. Brown; Ramon Canal; Binjie Cheng; Joan Figueras; Antonio González 001; Enric Herrero; S. Markov; Miguel Miranda; Peyman Pouyan; Tanausú Ramírez; et al. (IOLTS, 2011)

Accelerating microprocessor silicon validation by exposing ISA diversity. - Nikos Foutris; Dimitris Gizopoulos; Mihalis Psarakis; Xavier Vera; Antonio González 001 (MICRO, 2011)

Design of complex circuits using the Via-Configurable transistor array regular layout fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (SoCC, 2011)

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. - Ramon Canal; Antonio Rubio 001; A. Asenov; A. Brown; Miguel Miranda; Paul Zuber; Antonio González 001; Xavier Vera (FET, 2011)

Implementing End-to-End Register Data-Flow Continuous Self-Test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (IEEE Trans. Computers, 2011)

Setting an error detection infrastructure with low cost acoustic wave detectors. - Gaurang Upasani; Xavier Vera; Antonio González 001 (ISCA, 2012)

Capturing vulnerability variations for register files. - Javier Carretero; Enric Herrero; Matteo Monchiero; Tanausú Ramírez; Xavier Vera (DATE, 2013)

Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IOLTS, 2013)

Deconfigurable microprocessor architectures for silicon debug acceleration. - Nikos Foutris; Dimitris Gizopoulos; Xavier Vera; Antonio González 001 (ISCA, 2013)

Framework for economical error recovery in embedded cores. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IOLTS, 2014)

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. - Gaurang Upasani; Xavier Vera; Antonio González 001 (ISCA, 2014)

A Case for Acoustic Wave Detectors for Soft-Errors. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IEEE Trans. Computers, 2016)

Inside Tiger Lake: Intel's Next Generation Mobile Client CPU. - Xavier Vera (Hot Chips Symposium, 2020)