Xi Chen

Orcid: 0000-0002-7368-4787

Affiliations:
  • NVIDIA, Inc., Santa Clara, CA, USA
  • North Carolina State University, Raleigh, NC, USA (PhD 2011)


According to our database1, Xi Chen authored at least 12 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024

2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023

2022
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.
IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.
IEEE J. Solid State Circuits, 2013

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


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