Formal verification of embedded system designs at multiple levels of abstraction. - Xi Chen 024; Fang Chen; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2002)

Simulation Trace Verification for Quantitative Constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Embedded Software for SoC, 2003)

Case Studies of Model Checking for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (ACSD, 2003)

Automatic trace analysis for logic of constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DAC, 2003)

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DATE, 2003)

Verifying LOC based functional and performance constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2003)

Formal Verification for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Des. Autom. Embed. Syst., 2003)

Shared memory multiprocessor architectures for software IP routers. - Yan Luo 001; Laxmi Narayan Bhuyan; Xi Chen 024 (IEEE Trans. Parallel Distributed Syst., 2003)

Utilizing Formal Assertions for System Design of Network Processors. - Xi Chen 024; Yan Luo 001; Harry Hsieh; Laxmi N. Bhuyan; Felice Balarin (DATE, 2004)

Assertion-based power/performance analysis of network processor architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (HLDVT, 2004)

Assertion Based Verification and Analysis of Network Processor Architectures. - Xi Chen 024; Yan Luo 001; Harry Hsieh; Laxmi N. Bhuyan; Felice Balarin (Des. Autom. Embed. Syst., 2004)

Logic of constraints: a quantitative performance and functional constraint formalism. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Simulation based deadlock analysis for system level designs. - Xi Chen 024; Abhijit Davare; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (DAC, 2005)

Assertion-Based Design Exploration of DVS in Network Processor Architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (DATE, 2005)

Communication and co-simulation infrastructure for heterogeneous system integration. - Guang Yang 004; Xi Chen 024; Felice Balarin; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli (DATE, 2006)

Runtime Deadlock Analysis of SystemC Designs. - Eric Cheung; Piyush Satapathy; Vi Pham; Harry Hsieh; Xi Chen 024 (HLDVT, 2006)

Verification Approach of Metropolis Design Framework for Embedded Systems. - Xi Chen 024; Harry Hsieh; Felice Balarin (Int. J. Parallel Program., 2006)

Bridging RTL and gate: correlating different levels of abstraction for design debugging. - Eric Cheung; Xi Chen 024; Fur-Shing Tsai; Yu-Chin Hsu; Harry Hsieh (HLDVT, 2007)

Runtime deadlock analysis for system level design. - Eric Cheung; Xi Chen 024; Harry Hsieh; Abhijit Davare; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (Des. Autom. Embed. Syst., 2009)

A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. - Gary Miller; Bandana Bhattarai; Yu-Chin Hsu; Jay Dutt; Xi Chen 024; George Bakewell (DAC, 2011)