17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Zhong Gao; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (ISSCC, 2020)

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. - Jianglin Du; Teerachot Siriburanon; Xi Chen 070; Yizhe Hu; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing. - Enis Kobal; Teerachot Siriburanon; Xi Chen 070; Hieu Minh Nguyen; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE J. Solid State Circuits, 2023)

A Tiny 3.15-43.4-GHz 3.6-mW Divide-by-8 Ring-Based Injection-Locked Frequency Divider Using Multiphase Waveform Gating Technique. - Feifan Hong; Xi Chen 070; Anding Zhu; Robert Bogdan Staszewski; Teerachot Siriburanon (A-SSCC, 2024)

A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator. - Teerachot Siriburanon; Xi Chen 070; Chunxiao Liu; Jianglin Du; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2025)