FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. - Yijin Guan; Hao Liang 003; Ningyi Xu; Wenqiang Wang; Shaoshuai Shi; Xi Chen 107; Guangyu Sun 003; Wei Zhang 012; Jason Cong (FCCM, 2017)

FxpNet: Training a deep convolutional neural network in fixed-point representation. - Xi Chen 107; Xiaolin Hu; Hucheng Zhou; Ningyi Xu (IJCNN, 2017)

A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. - Xi Chen 107; An Guo 001; Xinbing Xu; Xin Si; Jun Yang 006 (APCCAS, 2022)

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications. - An Guo 001; Chen Xue; Xi Chen 107; Xin Si (CCF Trans. High Perform. Comput., 2022)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits. - Yiran Zhang; Bo Wang 023; Jinwu Chen; Xi Chen 107; Xin Si (MCSoC, 2023)

Evaluation Platform of Time-Domain Computing-in-Memory Circuits. - Yuyao Kong; Xi Chen 107; Xin Si; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Zhichao Liu; Feiran Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; Yuchen Tang; et al. (CICC, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. - Xi Chen 107; Yitong Zhao; An Guo 001; Jinwu Chen; Fangyuan Dong; Zhaoyang Zhang; Tianzhu Xiong; Bo Wang 023; Yuyao Kong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree. - Xing Wang; Tianhui Jiao; Shaochen Li; Yuchen Ma; Zhican Zhang; Zhichao Liu; Xi Chen 107; Xin Si (ASP-DAC, 2025)

AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM. - Yuanpeng Zhang; Xing Hu 010; Xi Chen 107; Zhihang Yuan; Cong Li; Jingchen Zhu; Zhao Wang; Chenguang Zhang; Xin Si; Wei Gao; Qiang Wu; Runsheng Wang; et al. (ISCA, 2025)

Modeling of Less-Significant Group Quantization for Hybrid CIM Architecture. - Shaochen Li; Xi Chen 107; Lingyi Kong; He Wang; Xing Wang; Yi Yang 001; Xin Si (ISCAS, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Yanqi Zhang; Feiran Liu; Zhichao Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; et al. (IEEE J. Solid State Circuits, 2025)