A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture. - Tian Xiang; Lei Zhao; Xi Jin 002; Tianqi Wang; Shaoping Chu; Cong Ma; Shubin Liu; Qi An; Xue Ben (FCCM, 2014)

Design of a Distributed Compressor for Astronomy SSD. - Bo Peng; Xi Jin 002; Tianqi Wang; Xueliang Du (FCCM, 2015)

RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations. - Tianqi Wang; Xi Jin 002; Bo Peng; Chuanjun Wang; Linlin Zheng (FCCM, 2016)

An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only). - Bo Peng; Tianqi Wang; Xi Jin 002; Chuanjun Wang (FPGA, 2016)

an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only). - Tianqi Wang; Bo Peng; Xi Jin 002 (FPGA, 2016)

An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). - Daolu Zha; Xi Jin 002; Tian Xiang (FPGA, 2016)

FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics. - Tianqi Wang; Linlin Zheng; Xi Jin 002; Bo Peng; Chuanjun Wang (FPT, 2016)

Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems. - Yuzhi Zhou; Xi Jin 002; Tian Xiang (FPT, 2016)

An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC. - Bo Peng; Tianqi Wang; Xi Jin 002; Chuanjun Wang (Int. J. Reconfigurable Comput., 2016)

A real-time global stereo-matching on FPGA. - Daolu Zha; Xi Jin 002; Tian Xiang (Microprocess. Microsystems, 2016)

An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address. - Teng Tian; Tianqi Wang; Xi Jin 002 (ISPA/IUCC, 2017)

A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions. - Daolu Zha; Xi Jin 002; Rui Shang; Pengfei Yang (ASAP, 2018)

An efficient resource-optimized learning prefetcher for solid state drives. - Rui Xu; Xi Jin 002; Linfeng Tao; Shuaizhi Guo; Zikun Xiang; Teng Tian (DATE, 2018)

Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment. - Zikun Xiang; Tianqi Wang; Tong Geng; Tian Xiang; Xi Jin 002; Martin C. Herbordt (HPEC, 2018)

Accelerating a radio astronomy correlator on FPGA. - Shuaizhi Guo; Linlin Zheng; Xi Jin 002 (ICACT, 2018)

A pipelined division for fixed operation using user-defined floating point. - Pengfei Yang; Daolu Zha; Xi Jin 002 (ICACT, 2018)

RP-Ring: A Heterogeneous Multi-FPGA Accelerator. - Shuaizhi Guo; Tianqi Wang; Linfeng Tao; Teng Tian; Zikun Xiang; Xi Jin 002 (Int. J. Reconfigurable Comput., 2018)

Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters. - Tianqi Wang; Tong Geng; Xi Jin 002; Martin C. Herbordt (ASAP, 2019)

FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications. - Tianqi Wang; Tong Geng; Xi Jin 002; Martin C. Herbordt (FCCM, 2019)

CINT - An Energy-efficient Mixed-signal In-Memory CNN Accelerator Based on NOR Flash Memory. - Linfeng Tao; Rui Xu; Teng Tian; Zikun Xiang; Yifei Li; Xi Jin 002; Jun Ren; Zhengda Li; Chenxia Li (MobiSys, 2019)

A Scalable Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Weight and Workload Balancing. - Tong Geng; Tianqi Wang; Ang Li 006; Xi Jin 002; Martin C. Herbordt (CoRR, 2019)

RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation. - Yuzhi Zhou; Xi Jin 002; Tian Xiang (BDET, 2020)

Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator. - Teng Tian; Xi Jin 002; Letian Zhao; Xiaotian Wang; Jie Wang; Wei Wu (DATE, 2020)

TB-DNN: A Thin Binarized Deep Neural Network with High Accuracy. - Jie Wang; Xi Jin 002; Wei Wu (ICACT, 2020)

BaPipe: Exploration of Balanced Pipeline Parallelism for DNN Training. - Letian Zhao; Rui Xu; Tianqi Wang; Teng Tian; Xiaotian Wang; Wei Wu; Chio-in Ieong; Xi Jin 002 (CoRR, 2020)

FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. - Yuzhi Zhou; Xi Jin 002; Tianqi Wang (Int. J. Reconfigurable Comput., 2020)

Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. - Yuzhi Zhou; Xi Jin 002; Tian Xiang; Daolu Zha (Microprocess. Microsystems, 2020)

A Real-Time Learning-Based Super-Resolution System on FPGA. - Daolu Zha; Xi Jin 002; Rui Shang; Pengfei Yang (Parallel Process. Lett., 2020)

FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters. - Tianqi Wang; Tong Geng; Ang Li 006; Xi Jin 002; Martin C. Herbordt (IEEE Trans. Computers, 2020)

Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator. - Qizhe Wu; Linfeng Tao; Huawen Liang; Wei Yuan 006; Teng Tian; Shuang Xue; Xi Jin 002 (HPEC, 2021)

A Gather Accelerator for GNNs on FPGA Platform. - Wei Yuan 006; Teng Tian; Huawen Liang; Xi Jin 002 (ICPADS, 2021)

A hybrid precision low power computing-in-memory architecture for neural networks. - Rui Xu; Linfeng Tao; Tianqi Wang; Xi Jin 002; Chenxia Li; Zhengda Li; Jun Ren (Microprocess. Microsystems, 2021)

An SSD-Based Accelerator for Singular Value Decomposition Recommendation Algorithm on Edge. - Wei Wu; Letian Zhao; Qizhe Wu; Xiaotian Wang; Teng Tian; Xi Jin 002 (HPEC, 2022)

HuGraph: Acceleration of GCN Training on Heterogeneous FPGA Clusters with Quantization. - Letian Zhao; Qizhe Wu; Xiaotian Wang; Teng Tian; Wei Wu; Xi Jin 002 (HPEC, 2022)

Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks. - Yuchen Gui; Boyi Wei; Wei Yuan 006; Xi Jin 002 (CoRR, 2022)

FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks. - Teng Tian; Letian Zhao; Xiaotian Wang; Qizhe Wu; Wei Yuan 006; Xi Jin 002 (Future Gener. Comput. Syst., 2022)

G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing. - Teng Tian; Xiaotian Wang; Letian Zhao; Wei Wu; Xuecang Zhang; Fangmin Lu; Tianqi Wang; Xi Jin 002 (J. Syst. Archit., 2022)

QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism. - Wei Yuan 006; Teng Tian; Qizhe Wu; Xi Jin 002 (J. Syst. Archit., 2022)

BaPipe: Balanced Pipeline Parallelism for DNN Training. - Letian Zhao; Rui Xu; Tianqi Wang; Teng Tian; Xiaotian Wang; Wei Wu; Chio-in Ieong; Xi Jin 002 (Parallel Process. Lett., 2022)

Exploration of Balanced Design in Resource-Constrained Edge Device for Efficient CNNs. - Xiaotian Wang; Teng Tian; Letian Zhao; Wei Wu; Xi Jin 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Dynamic Neural Network Accelerator for Multispectral detection Based on FPGA. - Xiaotian Wang; Letian Zhao; Wei Wu; Xi Jin 002 (ICACT, 2023)

Scheduling Memory Access Optimization for HBM Based on CLOS. - Shuang Xue; Huawei Liang; Qizhe Wu; Xi Jin 002 (ICACT, 2023)

MCANet: Multiscale Cross-Modality Attention Network for Multispectral Pedestrian Detection. - Xiaotian Wang; Letian Zhao; Wei Wu; Xi Jin 002 (MMM (1), 2023)

Degree-Aware Graph Neural Network Quantization. - Ziqin Fan; Xi Jin 002 (Entropy, 2023)

FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights. - Zerong He; Teng Tian; Qizhe Wu; Xi Jin 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling. - Yuchen Gui; Qizhe Wu; Wei Yuan 006; Huawen Liang; Xiaotian Wang; Xi Jin 002 (ASAP, 2024)

RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA. - Huawen Liang; Qizhe Wu; Wei Yuan 006; Teng Tian; Xi Jin 002 (FCCM, 2024)

Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. - Qizhe Wu; Letian Zhao; Yuchen Gui; Huawen Liang; Xiaotian Wang; Xi Jin 002 (FPGA, 2024)

Tightly-Coupled FPGA Accelerator for Molecular Dynamics Simulation: Hardware-Software Co-Design and Fine-Grained Task Management. - Zekang Cheng; Zerong He; Xi Jin 002 (HPEC, 2024)

HBM-Based Hardware Accelerator for GNN Sampling and Aggregation. - Yuchen Gui; Qizhe Wu; Wei Yuan 006; Huawen Liang; Xiaotian Wang; Xi Jin 002 (HPEC, 2024)

Task-Level Parallelism for the Multifrontal Method in Tightly Coupled CPU-FPGA Architectures. - Zerong He; Zekang Cheng; Zhongguang Xu; Xi Jin 002 (HPEC, 2024)

EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology. - Qizhe Wu; Yuchen Gui; Zhichen Zeng 002; Xiaotian Wang; Huawen Liang; Xi Jin 002 (ICCD, 2024)

Artificial Neural Network based Model for Power GaN HEMTs down to 4.2K. - Zikun Xiang; Haochen Zhang; Bolun Zeng; Lei Yang; Liling Qiu; Xi Jin 002; Guoping Guo; Chao Luo; Haiding Sun (ICTA, 2024)

EN-TensorCore: Advancing TensorCores Performance through Encoder-Based Methodology. - Qizhe Wu; Yuchen Gui; Zhichen Zeng 002; Xiaotian Wang; Huawen Liang; Xi Jin 002 (CoRR, 2024)

Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs. - Qizhe Wu; Huawen Liang; Yuchen Gui; Zhichen Zeng 002; Zerong He; Linfeng Tao; Xiaotian Wang; Letian Zhao; Zhaoxi Zeng; Wei Yuan 006; Wei Wu; Xi Jin 002 (HPCA, 2025)

GHVSA: Graph-based high-dimensional vector search accelerator. - Wei Yuan 006; Huawen Liang; Xi Jin 002 (J. Syst. Archit., 2025)

FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator. - Wei Yuan 006; Xi Jin 002 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

F3: An FPGA-Based Transformer Fine-Tuning Accelerator With Flexible Floating Point Format. - Zerong He; Xi Jin 002; Zhongguang Xu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)