Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. - Xi Wang 009; John D. Leidel; Yong Chen 001 (MEMSYS, 2016)

OpenSoC system architect: An open toolkit for building soft-cores on FPGAs. - Farzad Fatollahi-Fard; David Donofrio; John Shalf; John D. Leidel; Xi Wang 009; Yong Chen 001 (FPL, 2017)

OpenMP Memkind: An Extension for Heterogeneous Physical Memories. - Xi Wang 009; John D. Leidel; Yong Chen 001 (ICPP Workshops, 2017)

Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications. - John D. Leidel; Xi Wang 009; Yong Chen 001 (IA3@SC, 2017)

GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing. - John D. Leidel; Xi Wang 009; Yong Chen 001 (HPEC, 2018)

Memory Coalescing for Hybrid Memory Cube. - Xi Wang 009; John D. Leidel; Yong Chen 001 (ICPP, 2018)

xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory. - John D. Leidel; Xi Wang 009; Frank Conlon; Yong Chen 001; David Donofrio; Farzad Fatollahi-Fard; Kurt Keville (MCHPC@SC, 2018)

POSTER: Memory Hotspot Optimization for Data-Intensive Applications. - Xi Wang 009; Jie Li 057; Antonino Tumeo; John D. Leidel; Yong Chen 001 (PACT, 2019)

MAC: Memory Access Coalescer for 3D-Stacked Memory. - Xi Wang 009; Antonino Tumeo; John D. Leidel; Jie Li 057; Yong Chen 001 (ICPP, 2019)

Collective Communication for the RISC-V xBGAS ISA Extension. - Brody Williams; Xi Wang 009; John D. Leidel; Yong Chen 001 (ICPP Workshops, 2019)

PIMS: a lightweight processing-in-memory accelerator for stencil computations. - Jie Li 057; Xi Wang 009; Antonino Tumeo; Brody Williams; John D. Leidel; Yong Chen 001 (MEMSYS, 2019)

Remote Atomic Extension (RAE) for Scalable High Performance Computing. - Xi Wang 009; Brody Williams; John D. Leidel; Alan Ehret; Michel A. Kinsy; Yong Chen 001 (DAC, 2020)

PAC: Paged Adaptive Coalescer for 3D-Stacked Memory. - Xi Wang 009; John D. Leidel; Brody Williams; Yong Chen 001 (HPDC, 2020)

CircusTent: A Benchmark Suite for Atomic Memory Operations. - Brody Williams; John D. Leidel; Xi Wang 009; David Donofrio; Yong Chen 001 (MEMSYS, 2020)

Toward a Microarchitecture for Efficient Execution of Irregular Applications. - John D. Leidel; Xi Wang 009; Brody Williams; Yong Chen 001 (ACM Trans. Parallel Comput., 2020)

DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model. - Zach Hansen; Brody Williams; John D. Leidel; Xi Wang 009; Yong Chen 001 (HPEC, 2021)

xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. - Xi Wang 009; John D. Leidel; Brody Williams; Alan Ehret; Miguel Mark; Michel A. Kinsy; Yong Chen 001 (IPDPS, 2021)

CircusTent: A Tool for Measuring the Performance of Atomic Memory Operations on Emerging Architectures. - Brody Williams; John D. Leidel; Xi Wang 009; David Donofrio; Yong Chen 001 (OpenSHMEM, 2021)

HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory. - Xi Wang 009; Antonino Tumeo; John D. Leidel; Jie Li 057; Yong Chen 001 (IEEE Trans. Computers, 2021)

Differential Game with Mixed Strategies: A Weak Approximation Approach. - Tao Xu; Xi Wang 009; Jianping He 001 (CDC, 2023)

Make Each Iteration Count. - Yuchen Hu; Ke Xu; Jialin Sun; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ACM TUR-C, 2024)

ChatCPU: An Agile CPU Design and Verification Platform with LLM. - Xi Wang 009; Gwok-Waa Wan; Sam-Zaak Wong; Layton Zhang; Tianyang Liu; Qi Tian; Jianmin Ye (DAC, 2024)

Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability. - Gwok-Waa Wan; Sam-Zaak Wong; Xi Wang 009 (ACM Great Lakes Symposium on VLSI, 2024)

MEIC: Re-thinking RTL Debug Automation using LLMs. - Ke Xu; Jialin Sun; Yuchen Hu; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ICCAD, 2024)

Large Language Model for Verilog Generation with Golden Code Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Xi Wang 009; Zhe Jiang 004; Nan Guan (CoRR, 2024)

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. - Bingkun Yao; Ning Wang 071; Jie Zhou; Xi Wang 009; Hong Gao; Zhe Jiang 004; Nan Guan (CoRR, 2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs. - Yuchen Hu; Junhao Ye; Ke Xu; Jialin Sun; Shiyue Zhang; Xinyao Jiao; Dingrong Pan; Jie Zhou; Ning Wang 071; Weiwei Shan; Xinwei Fang; Xi Wang 009; et al. (CoRR, 2024)

A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. - Cai Li; Haochang Zhi; Kaiyue Yang; Junyi Qian; Zhihao Yan; Lixuan Zhu; Chao Chen; Xi Wang 009; Weiwei Shan (IEEE J. Solid State Circuits, 2024)

DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits. - Yuxuan Du; Junyi Qian; Zhengguo Shen; Chengjun Wu; Weiwei Shan; Xi Wang 009 (IEEE J. Solid State Circuits, 2024)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. - Junhao Ye; Yuchen Hu; Ke Xu; Dingrong Pan; Qichun Chen; Jie Zhou; Shuai Zhao 004; Xinwei Fang; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection. - Juxin Niu; Xiangfeng Liu; Dan Niu; Xi Wang 009; Zhe Jiang 004; Nan Guan (CoRR, 2025)

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. - Gwok-Waa Wan; Shengchu Su; Ruihu Wang; Qixiang Chen; Sam-Zaak Wong; Mengnv Xing; Hefei Feng; Yubo Wang; Yinan Zhu; Jingyi Zhang; Jianmin Ye; Xinlai Wan; et al. (CoRR, 2025)