The design-for-testability features of a general purpose microprocessor. - Da Wang; Xiaoxin Fan; Xiang Fu 007; Hui Liu; Ke Wen; Rui Li; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ITC, 2007)

Robust test generation for power supply noise induced path delay faults. - Xiang Fu 007; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ASP-DAC, 2008)

Localized random access scan: Towards low area and routing overhead. - Yu Hu 001; Xiang Fu 007; Xiaoxin Fan; Hideo Fujiwara (ASP-DAC, 2008)

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Testable Critical Path Selection Considering Process Variation. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

Testable Path Selection and Grouping for Faster Than At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)