SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li 147; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li 147; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree. - Xin Si; Fangyuan Dong; Shengnan He; Yuhui Shi; Anran Yin; Hui Gao; Xiang Li 147 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 22-nm 264-GOPS/mm2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs. - Feiran Liu; Anran Yin; Chen Xue; Bo Wang 023; Zhongyuan Feng; Han Liu; Xiang Li 147; Hui Gao; Tianzhu Xiong; Xin Si (IEEE Trans. Very Large Scale Integr. Syst., 2024)