A Resources-Efficient Configurable Accelerator for Deep Convolutional Neural Networks. - Xianghong Hu 001; Yuhang Zeng; Zicong Li; Xin Zheng 001; Shuting Cai; Xiaoming Xiong (IEEE Access, 2019)

The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System. - Xin Zheng 001; Chongyao Xu; Xianghong Hu 001; Yun Zhang 001; Xiaoming Xiong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT. - Xianghong Hu 001; Hongmin Huang; Xin Zheng 001; Yuan Liu 022; Xiaoming Xiong (IEICE Trans. Electron., 2021)

Subgraph feature extraction based on multi-view dictionary learning for graph classification. - Xin Zheng 001; Shouzhi Liang; Bo Liu 002; Xiaoming Xiong; Xianghong Hu 001; Yuan Liu 022 (Knowl. Based Syst., 2021)

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. - Xiaomeng Wang; Xuejiao Liu; Xianghong Hu 001; Xiaopeng Zhong; Xizi Chen; Yu Liu 007; Patrick Kong; Fengshi Tian; Chi-Ying Tsui (AICAS, 2022)

An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs. - Hongmin Huang; Xueming Li 001; Yadong Qin; Xianghong Hu 001; Xiaoming Xiong (HP3C, 2022)

SDQ: Stochastic Differentiable Quantization with Mixed Precision. - Xijie Huang; Zhiqiang Shen; Shichao Li 002; Zechun Liu; Xianghong Hu 001; Jeffry Wicaksana; Eric P. Xing; Kwang-Ting Cheng (ICML, 2022)

A high speed processor for elliptic curve cryptography over NIST prime field. - Xianghong Hu 001; Xueming Li 001; Xin Zheng 001; Yuan Liu 022; Xiaoming Xiong (IET Circuits Devices Syst., 2022)

An efficient loop tiling framework for convolutional neural network inference accelerators. - Hongmin Huang; Xianghong Hu 001; Xueming Li 001; Xiaoming Xiong (IET Circuits Devices Syst., 2022)

A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator. - Xueming Li 001; Hongmin Huang; Taosheng Chen; Huaien Gao; Xianghong Hu 001; Xiaoming Xiong (Microelectron. J., 2022)

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization. - Xianghong Hu 001; Xueming Li 001; Hongmin Huang; Xin Zheng 001; Xiaoming Xiong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad. - Xianghong Hu 001; Xuejiao Liu; Yu Liu 007; Haowei Zhang; Xijie Huang; Xihao Guan; Luhong Liang; Chi-Ying Tsui; Xiaoming Xiong; Kwang-Ting Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. - Xianghong Hu 001; Hongmin Huang; Xueming Li 001; Xin Zheng 001; Qinyuan Ren; Jingyu He; Xiaoming Xiong (ACM Trans. Embed. Comput. Syst., 2023)

An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits. - Xin Zheng 001; Shaofen Zeng; Yongfeng Zhong; Chenyu Huang; Xianghong Hu 001; Xiaoming Xiong (IEEE Embed. Syst. Lett., 2024)

A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator. - Yuanmiao Lin; Shansen Fu; Xueming Li 001; Chaoming Yang; Rongfeng Li 001; Hongmin Huang; Xianghong Hu 001; Shuting Cai; Xiaoming Xiong (IEEE Comput. Archit. Lett., 2025)

A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability. - Rongfeng Li 001; Xueming Li 001; Chaoming Yang; Xianghong Hu 001; Yuanmiao Lin; Shansen Fu; Hongmin Huang; Shuting Cai; Xiaoming Xiong (IEICE Electron. Express, 2025)

An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks. - Xianghong Hu 001; Shansen Fu; Yuanmiao Lin; Xueming Li 001; Chaoming Yang; Rongfeng Li 001; Hongmin Huang; Shuting Cai; Xiaoming Xiong (J. Syst. Archit., 2025)

An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization. - Yuanmiao Lin; Zhaozhang Feng; Xueming Li 001; Hongmin Huang; Ruidian Zhan; Xianghong Hu 001; Shuting Cai; Xiaoming Xiong (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees. - Xianghong Hu 001; Chaoming Yang; Xueming Li 001; Rongfeng Li 001; Yuanmiao Lin; Shansen Fu; Hongmin Huang; Shuting Cai; Xiaoming Xiong (ACM Trans. Embed. Comput. Syst., 2025)