A Resources-Efficient Configurable Accelerator for Deep Convolutional Neural Networks. - Xianghong Hu; Yuhang Zeng; Zicong Li; Xin Zheng 001; Shuting Cai; Xiaoming Xiong (IEEE Access, 2019)

Modeling and Simulation of Energy Hub Considering Solid Oxide Fuel Cell and Power to Gas. - Jun Jin 009; Biao Yang; Xianghong Hu; Binhua Yao; Jin Xie; Wenjie Zhang; Dan Zhou (IECON, 2020)

Bayesian weighted Mendelian randomization for causal inference based on summary statistics. - Jia Zhao; Jingsi Ming; Xianghong Hu; Gang Chen; Jin Liu 011; Can Yang 002 (Bioinform., 2020)

The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System. - Xin Zheng 001; Chongyao Xu; Xianghong Hu; Yun Zhang 001; Xiaoming Xiong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT. - Xianghong Hu; Hongmin Huang; Xin Zheng 001; Yuan Liu 022; Xiaoming Xiong (IEICE Trans. Electron., 2021)

Subgraph feature extraction based on multi-view dictionary learning for graph classification. - Xin Zheng 001; Shouzhi Liang; Bo Liu 002; Xiaoming Xiong; Xianghong Hu; Yuan Liu 022 (Knowl. Based Syst., 2021)

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. - Xiaomeng Wang; Xuejiao Liu; Xianghong Hu; Xiaopeng Zhong; Xizi Chen; Yu Liu 007; Patrick Kong; Fengshi Tian; Chi-Ying Tsui (AICAS, 2022)

An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs. - Hongmin Huang; Xueming Li; Yadong Qin; Xianghong Hu; Xiaoming Xiong (HP3C, 2022)

SDQ: Stochastic Differentiable Quantization with Mixed Precision. - Xijie Huang; Zhiqiang Shen; Shichao Li 002; Zechun Liu; Xianghong Hu; Jeffry Wicaksana; Eric P. Xing; Kwang-Ting Cheng (ICML, 2022)

XPXP: improving polygenic prediction by cross-population and cross-phenotype analysis. - Jiashun Xiao; Mingxuan Cai; Xianghong Hu; Xiang Wan; Gang Chen; Can Yang 002 (Bioinform., 2022)

A high speed processor for elliptic curve cryptography over NIST prime field. - Xianghong Hu; Xueming Li; Xin Zheng 001; Yuan Liu 022; Xiaoming Xiong (IET Circuits Devices Syst., 2022)

An efficient loop tiling framework for convolutional neural network inference accelerators. - Hongmin Huang; Xianghong Hu; Xueming Li; Xiaoming Xiong (IET Circuits Devices Syst., 2022)

A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator. - Xueming Li; Hongmin Huang; Taosheng Chen; Huaien Gao; Xianghong Hu; Xiaoming Xiong (Microelectron. J., 2022)

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization. - Xianghong Hu; Xueming Li; Hongmin Huang; Xin Zheng 001; Xiaoming Xiong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad. - Xianghong Hu; Xuejiao Liu; Yu Liu 007; Haowei Zhang; Xijie Huang; Xihao Guan; Luhong Liang; Chi-Ying Tsui; Xiaoming Xiong; Kwang-Ting Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. - Xianghong Hu; Hongmin Huang; Xueming Li; Xin Zheng 001; Qinyuan Ren; Jingyu He; Xiaoming Xiong (ACM Trans. Embed. Comput. Syst., 2023)

An End-to-End Deep-Learning-Based Indirect Time-of-Flight Image Signal Processor. - An-Nan Xiong; Yuzhong Jiao; Xuejiao Liu; Manto Yung; Xianghong Hu; Luhong Liang; Jie Yuan; Mansun Chan (ISCAS, 2024)

MFAI: A Scalable Bayesian Matrix Factorization Approach to Leveraging Auxiliary Information. - Zhiwei Wang; Fa Zhang; Cong Zheng; Xianghong Hu; Mingxuan Cai; Can Yang 002 (J. Comput. Graph. Stat., 2024)

An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits. - Xin Zheng 001; Shaofen Zeng; Yongfeng Zhong; Chenyu Huang; Xianghong Hu; Xiaoming Xiong (IEEE Embed. Syst. Lett., 2024)

A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator. - Yuanmiao Lin; Shansen Fu; Xueming Li; Chaoming Yang; Rongfeng Li; Hongmin Huang; Xianghong Hu; Shuting Cai; Xiaoming Xiong (IEEE Comput. Archit. Lett., 2025)

A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability. - Rongfeng Li; Xueming Li; Chaoming Yang; Xianghong Hu; Yuanmiao Lin; Shansen Fu; Hongmin Huang; Shuting Cai; Xiaoming Xiong (IEICE Electron. Express, 2025)

An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks. - Xianghong Hu; Shansen Fu; Yuanmiao Lin; Xueming Li; Chaoming Yang; Rongfeng Li; Hongmin Huang; Shuting Cai; Xiaoming Xiong (J. Syst. Archit., 2025)