Xianghui Xie

Orcid: 0000-0002-2661-0179

Affiliations:
  • Jiangnan Institute of Computing Technology, State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi, China


According to our database1, Xianghui Xie authored at least 24 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Performance-Aware Model for Sparse Matrix-Matrix Multiplication on the Sunway TaihuLight Supercomputer.
IEEE Trans. Parallel Distributed Syst., 2019

FPGA应用于高性能计算的研究现状和未来挑战 (Research Advances and Future Challenges of FPGA-based High Performance Computing).
计算机科学, 2019

2018
Exploring high-performance processor architecture beyond the exascale.
Frontiers Inf. Technol. Electron. Eng., 2018

2017
RBPCCM: Relax Blocking Parallel Collective Communication Mechanism Base on Hardware with Scalability.
Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

A High-Performance Accelerator for Floating-Point Matrix Multiplication.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

2016
Implementing Molecular Dynamics Simulation on Sunway TaihuLight System.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015
GF(2m)上椭圆曲线标量乘的硬件结构实现 (Hardware Implementation of Scalar Multiplication on Elliptic Curves over GF(2m)).
计算机科学, 2015

面向定制结构的稀疏矩阵分块方法 (Sparse Matrix Blocking Method for Custom Architecture).
计算机科学, 2015

Cooperative Computing Techniques for a Deeply Fused and Heterogeneous Many-Core Processor Architecture.
J. Comput. Sci. Technol., 2015

A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Thread ID based power reduction mechanism for multi-thread shared set-associative caches.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

2014
A new parallel lattice reduction algorithm for BKZ reduced bases.
Sci. China Inf. Sci., 2014

SRS: A Split-Range Shared Memory Consistency Model for Thousand-Core Processors.
Proceedings of the Advanced Computer Architecture - 10th Annual Conference, 2014

2013
High-Performance Architecture for the Conjugate Gradient Solver on FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
Parallelizing sparse LU decomposition on FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2010
Evolution of supercomputers.
Frontiers Comput. Sci. China, 2010

A parallel logic simulation framework: study, implementation, and performance.
Proceedings of the 2010 Spring Simulation Multiconference, 2010

2009
ArchSim: A System-Level Parallel Simulation Platform for the Architecture Design of High Performance Computer.
J. Comput. Sci. Technol., 2009

A Parallel SystemC Environment: ArchSC.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

2007
A Data Access Scheme of Heterogeneous Data Resource in Grid.
Proceedings of the Grid and Cooperative Computing, 2007

2006
Application of Grid Computing in Petroleum Exploration.
Proceedings of the Grid and Cooperative Computing Workshops, 2006

Application of Grid Technology in Multi-Objective Aircraft Optimization System.
Proceedings of the 10th International Conference on CSCW in Design, 2006

2005
System Software for China National Grid.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2005


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