A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme. - Mingchao Jian; Jiwei Zheng; Xiangjian Kong; Meng Yuan; Chunhua Zhang; Chunbing Guo; Bo Sun (Microelectron. J., 2022)

A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch. - Xiangjian Kong; Ding Qiu; Mingchao Jian; Chunbing Guo; Kai Xu (ASICON, 2023)

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter. - Ding Qiu; Xiangjian Kong; Mingchao Jian; Jiwei Zheng; Chunbing Guo (Microelectron. J., 2023)

A 19.58-to-21.38-GHz Low-Power Quad-Core VCO with Compact 3rd-Order Q-boost Inductors Achieving -191.8-dBc/Hz FoM and -205.4-dBc/Hz FoMA. - Xiangjian Kong; Shuai Deng; Zhao Zhang 004 (A-SSCC, 2024)

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement. - Xiangjian Kong; Kai Xu; Robert Bogdan Staszewski; Mingchao Jian; Chunbing Guo (VLSI Technology and Circuits, 2024)

RFIC Reuse Techniques to Enable Ultra-Low-Power IoT: A Tutorial. - Kai Xu; Xiangjian Kong; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 73-dB-SNDR 2nd-Order Noise-Shaping SAR With a Low-Noise Time-Domain Comparator. - Mingchao Jian; Jiwei Zheng; Xiangjian Kong; Bo Sun; Chunbing Guo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. - Xinyu Shen; Zhao Zhang 004; Yixi Li; Junjie Chen; Xiangjian Kong; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ISSCC, 2025)

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique. - Xiangjian Kong; Kai Xu; Huanlin Xie; Mingchao Jian; Hao Lian; Robert Bogdan Staszewski; Chunbing Guo (IEEE J. Solid State Circuits, 2025)