Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router. - Xianglong Ren; Deyuan Gao; Xiaoya Fan; Jianfeng An; Tao Yao (CIT, 2012)

Three-Operand Floating-Point Adder. - Tao Yao; Deyuan Gao; Xiaoya Fan; Xianglong Ren (CIT, 2012)

High-Speed Transcendental Function Operation Unit Design. - Ze Tian; Feihu Fan; Jun Zhang; Xianglong Ren; Wei Yang (CSCloud/EdgeCom, 2022)

Survey of Shared Register File design for Unified Shader Array in GPUs. - Ze Tian; Jun Zhang; Xianglong Ren; Feihu Fan; Chen Yue (CSCloud/EdgeCom, 2022)

Design of Shared Register File of GPU Unified Shader Array. - Ze Tian; Xianglong Ren; Jun Zhang; Feihu Fan; Yue Chen (CSCloud/EdgeCom, 2022)