A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. - Qirui Ren; Qiang Huo; Zhisheng Chen; Qi Gao; Yiming Wang; Yiming Yang; Hao Wu 084; Xiangqu Fu; Xiaoxin Xu; Qing Luo; Jianfeng Gao 005; Chengying Chen; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. - Xiangqu Fu; Qirui Ren; Hao Wu 084; Feibin Xiang; Qing Luo; Jinshan Yue; Yong Chen 005; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. - Zeyu Guo 002; Jinshan Yue; Shengzhe Yan; Zhuoyu Dai; Xiangqu Fu; Zhaori Cong; Zening Niu; Ke Hu; Lihua Xu; Jiawei Wang; Lingfei Wang; Guanhua Yang; et al. (DAC, 2024)

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xiangqu Fu; Qirui Ren; Qing Luo; Pui-In Mak; Xinghua Wang; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. - Zhuoyu Dai; Feibin Xiang; Xiangqu Fu; Yifan He 003; Wenyu Sun; Yongpan Liu; Guanhua Yang; Feng Zhang 014; Jinshan Yue; Ling Li 013 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. - Xiangqu Fu; Jinshan Yue; Muhammad Faizan; Zhi Li 062; Qiang Huo; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)