A Comparative Study of Large-Scale Cluster Workload Traces via Multiview Analysis. - Li Ruan; Xiangrong Xu 002; Limin Xiao 001; Feng Yuan; Yin Li; Dong Dai 001 (HPCC/SmartCity/DSS, 2019)

Evaluating performance variations cross cloud data centres using multiview comparative workload traces analysis. - Li Ruan; Xiangrong Xu 002; Limin Xiao 001; Lei Ren 001; Nasro Min-Allah; Yunzhi Xue (Connect. Sci., 2022)

ReDas: Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array. - Meng Han; Liang Wang 020; Limin Xiao 001; Tianhao Cai; Zeyu Wang; Xiangrong Xu 002; Chenhao Zhang (CoRR, 2023)

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache with Aggregated Tag Array. - Xiangrong Xu 002; Liang Wang 020; Limin Xiao 001; Lei Liu 037; Xilong Xie; Meng Han; Hao Liu 107 (CoRR, 2023)

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds. - Meng Han; Liang Wang 020; Limin Xiao 001; Hao Zhang 205; Chenhao Zhang; Xiangrong Xu 002; Jianfeng Zhu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

BitNN: A Bit-Serial Accelerator for K-Nearest Neighbor Search in Point Clouds. - Meng Han; Liang Wang 020; Limin Xiao 001; Hao Zhang 205; Tianhao Cai; Jiale Xu; Yibo Wu; Chenhao Zhang; Xiangrong Xu 002 (ISCA, 2024)

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array. - Xiangrong Xu 002; Liang Wang 020; Limin Xiao 001; Lei Liu 037; Yuanqiu Lv; Xilong Xie; Meng Han; Hao Liu 107 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array. - Meng Han; Liang Wang 020; Limin Xiao 001; Tianhao Cai; Zeyu Wang; Xiangrong Xu 002; Chenhao Zhang (IEEE Trans. Computers, 2024)

FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs. - Xilong Xie; Liang Wang 020; Limin Xiao 001; Meng Han; Lin Sun; Shuai Zheng; Xiangrong Xu 002 (DATE, 2025)

Swift-Sim: A Modular and Hybrid GPU Architecture Simulation Framework. - Xiangrong Xu 002; Yuanqiu Lv; Liang Wang 020; Limin Xiao 001; Meng Han; Runnan Shen; Jinquan Wang (DATE, 2025)

Amove: Accelerating LLMs through Mitigating Outliers and Salient Points via Fine-Grained Grouped Vectorized Data Type. - Xilong Xie; Liang Wang 020; Limin Xiao 001; Meng Han; Lei Liu 037; Xiangrong Xu 002; Jinquan Wang; Zhen Song; Xiaojian Liao (MICRO, 2025)

Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache. - Xiangrong Xu 002; Liang Wang 020; Limin Xiao 001; Lei Liu 037; Zihao Zhou; Yuanqiu Lv; Li Ruan; Xilong Xie; Meng Han; Xiaojian Liao (J. Syst. Archit., 2025)

DeepCEE: Efficient Cross-Region Model Distributed Training System under Heterogeneous GPUs and Networks. - Jinquan Wang; Xiaojian Liao; Xuzhao Liu; Jiashun Suo; Zhisheng Huo; Chenhao Zhang; Xiangrong Xu 002; Runnan Shen; Xilong Xie; Limin Xiao 001 (CoRR, 2025)

A two-stage data placement strategy for cloud-edge-device collaborative environment. - Runnan Shen; Jinquan Wang; Zhisheng Huo; Limin Xiao 001; Shengyang Tan; Yuntong Li; Lun Li; Xiangrong Xu 002; Liang Wang 020 (Comput. Commun., 2026)