A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. - Xiangxun Zhan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. - Xiangxun Zhan; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)